公开(公告)号：US20220157754A1

公开(公告)日：2022-05-19

申请号：US17381782

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong PARK ,  Chanho KIM ,  Pansuk KWAK ,  Daeseok BYEON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L25/00

Abstract: A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

公开(公告)号：US20210366892A1

公开(公告)日：2021-11-25

申请号：US17393934

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho KIM ,  Dongku KANG ,  Daeseok BYEON

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/00

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

公开(公告)号：US20210066320A1

公开(公告)日：2021-03-04

申请号：US16944733

申请日：2020-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho KIM ,  Dongku KANG ,  Daeseok BYEON

IPC: H01L27/112 ,  H01L27/24 ,  H01L27/108 ,  H01L27/11585

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

公开(公告)号：US20210066280A1

公开(公告)日：2021-03-04

申请号：US16942854

申请日：2020-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong PARK ,  Chanho KIM ,  Daeseok BYEON

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: A memory device includes a memory cell chip, a peripheral circuit chip, and a routing wire. The memory cell chip includes a memory cell array disposed on a first substrate, and a first metal pad on a first uppermost metal layer. The peripheral circuit chip includes circuit devices disposed on a second substrate, and a second metal pad on a second uppermost metal layer of the peripheral circuit chip. The memory cell chip and the peripheral circuit chip are vertically connected to each other by the first metal pad and the second metal pad in a bonding area. The routing wire is electrically connected to the peripheral circuit and is disposed in the first uppermost metal layer or the second uppermost metal layer and is disposed in a non-bonding area in which the memory cell chip and the peripheral circuit chip are not electrically connected to each other.