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公开(公告)号：US20210066276A1
公开(公告)日：2021-03-04
申请号：US16806030
申请日：2020-03-02
发明人： Chanho KIM , Dongku KANG , Daeseok BYEON
摘要： An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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公开(公告)号：US20210036008A1
公开(公告)日：2021-02-04
申请号：US16809059
申请日：2020-03-04
发明人： Kyunghwa YUN , Chanho KIM , Dongku KANG
IPC分类号： H01L27/11582 , H01L27/11565
摘要： A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.
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公开(公告)号：US20230207549A1
公开(公告)日：2023-06-29
申请号：US18179056
申请日：2023-03-06
发明人： Chanho KIM , Dongku KANG , Daeseok BYEON
CPC分类号： H01L25/18 , H01L23/481 , H01L24/08 , H01L2224/05647 , H01L2224/08145 , H01L24/05
摘要： An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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公开(公告)号：US20210074596A1
公开(公告)日：2021-03-11
申请号：US16846724
申请日：2020-04-13
发明人： Taehyo KIM , Daeseok BYEON , Chanho KIM
IPC分类号： H01L21/66 , G01N21/95 , H01L23/544
摘要： A semiconductor device includes a semiconductor die, a semiconductor integrated circuit, an outer crack detection structure, a plurality of inner crack detection structures and a plurality of path selection circuits. The semiconductor die includes a central region and an edge region surrounding the central region. The semiconductor integrated circuit is in a plurality of sub regions of the central region. The outer crack detection structure is in the edge region. The plurality of inner crack detection structures are respectively in the plurality of sub regions, respectively. The path selection circuits are configured to control an electrical connection between the outer crack detection structure and the plurality of inner crack detection structures. A crack in the central region in addition to a crack in the edge region may be detected efficiently through selective electrical connection of the outer crack detection structure and the inner crack detection structures.
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公开(公告)号：US20210118487A1
公开(公告)日：2021-04-22
申请号：US16871815
申请日：2020-05-11
发明人： Chanho KIM , Daeseok BYEON , Hyunsurk RYU
IPC分类号： G11C11/4093 , G11C11/4094 , G11C11/408 , G11C5/06
摘要： A flash memory device includes: first pads; second pads; third pads; a memory cell array; a row decoder block; a buffer block that stores a command and an address received from an external semiconductor chip through the first pads and provides the address to the row decoder block; a page buffer block that is connected to the memory cell array through bit lines, is connected to the third pads through data lines, and exchanges data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block that receives the command from the buffer block, receives control signals from the external semiconductor chip through the second pads, and controls the row decoder block and the page buffer block based on the received command and the received control signals.
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公开(公告)号：US20210005593A1
公开(公告)日：2021-01-07
申请号：US17025300
申请日：2020-09-18
发明人： Youn-Yeol LEE , Chanho KIM
IPC分类号： H01L25/18 , H01L25/065 , H01L23/00
摘要： A memory device includes a peripheral circuit layer, a first memory layer provided on the peripheral circuit layer, an inter-metal layer provided on the first memory layer, and a second memory layer provided on the inter-metal layer. The peripheral circuit layer includes a first substrate and a peripheral circuit provided on the first substrate. The first memory layer includes a first memory structure electrically connected to the peripheral circuit through metal bonding pads. The inter-metal layer includes intermediate pads electrically connected to the peripheral circuit through metal bonding pads. The second memory layer includes a second memory structure electrically connected with the intermediate pads and a second substrate provided on the second memory structure. The peripheral circuit, the first memory structure, and the second structure are provided between the first substrate and the second substrate.
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公开(公告)号：US20220180917A1
公开(公告)日：2022-06-09
申请号：US17682100
申请日：2022-02-28
发明人： Chanho KIM , Daeseok BYEON , Hyunsurk RYU
IPC分类号： G11C11/4093 , G11C11/4094 , G11C5/06 , G11C11/408 , G11C16/04 , G11C16/08
摘要： Flash memory device includes: first pads to be bonded to external semiconductor chip, to receive at least one of command, address and control signals; second pads to be bonded to external semiconductor chip; memory cell array including memory cells; a row decoder block connected to memory cell array through word lines, to select one of word lines based on address provided to row decoder block; a buffer block to store command and address and provide address to row decoder block; a page buffer block connected to memory cell array through bit lines, connected to second pads through data lines without passing through buffer block, and configured to exchange data signals with external semiconductor chip through data lines and second pads; and a control logic block configured to receive command from buffer block, to receive control signals from external semiconductor chip, and to control row decoder block and page buffer block.
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公开(公告)号：US20220102335A1
公开(公告)日：2022-03-31
申请号：US17545522
申请日：2021-12-08
发明人： Jooyong PARK , Chanho KIM , Daeseok BYEON
IPC分类号： H01L25/18 , H01L25/065 , H01L23/00
摘要： A memory device includes first and second chips. The first chip includes a memory cell array disposed on a first substrate, and first metal pads on a first uppermost metal layer of the first chip. The second chip includes peripheral circuits disposed on a second substrate, and second metal pads on a second uppermost metal layer of the second chip, the peripheral circuits operating the memory cell array. A first metal pad and a second metal pad are connected in a first area, the first metal pads being connected to the memory cell array and the second metal pad being connected to the peripheral circuits. A further first metal pad and a further second metal pad are connected in a second area, the further first metal pad being not connected to the memory cell array and the further second metal pad being connected to the peripheral circuits.
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公开(公告)号：US20210043639A1
公开(公告)日：2021-02-11
申请号：US16814491
申请日：2020-03-10
发明人： Kyunghwa YUN , Pansuk KWAK , Chanho KIM , Dongku KANG
IPC分类号： H01L27/11556 , G11C5/02 , G11C5/06 , H01L27/11582
摘要： A memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating through the wordlines; and a cell contact region including cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction. Each of the first and second cell contact regions includes first pads having different lengths to each other in the first direction and second pads different from the first pads, and the cell contacts are connected to the wordlines in the first pads. The number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region.
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公开(公告)号：US20200321349A1
公开(公告)日：2020-10-08
申请号：US16662073
申请日：2019-10-24
发明人： Taehong KWON , Chanho KIM , Daeseok BYEON , Pansuk KWAK , Chiweon YOON
IPC分类号： H01L27/11573 , H01L27/11582 , H01L29/94 , H01L29/78
摘要： A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.
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