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公开(公告)号：US20240284673A1
公开(公告)日：2024-08-22
申请号：US18583467
申请日：2024-02-21
发明人： Takuya FUTATSUYAMA , Daeseok BYEON
IPC分类号： H10B43/27 , H01L23/00 , H01L23/48 , H01L25/065 , H10B43/35 , H10B43/40 , H10B61/00 , H10B63/10
CPC分类号： H10B43/27 , H01L23/481 , H01L24/08 , H01L25/0657 , H10B43/35 , H10B43/40 , H01L2224/08145 , H01L2924/1438 , H10B61/20 , H10B63/10
摘要： A memory device is disclosed. The memory device includes a first cell region including first memory strings, a second cell region attached to the first cell region and including second memory strings, and a peripheral circuit region attached to the first cell region and including a peripheral circuit configured to control the first and second memory strings, the first cell region including a low-level bit line electrically connected to the first memory strings, a low-level bonding pad provided between the peripheral circuit region and the first cell region, a low-level connection via connected to the low-level bonding pad, a high-level bonding pad provided between the first and second cell regions, the second cell region including a high-level bit line electrically connected to the second memory strings, and a high-level connection via connected to the high-level bonding pad and being laterally offset from the low-level connection via.
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公开(公告)号：US20210118487A1
公开(公告)日：2021-04-22
申请号：US16871815
申请日：2020-05-11
发明人： Chanho KIM , Daeseok BYEON , Hyunsurk RYU
IPC分类号： G11C11/4093 , G11C11/4094 , G11C11/408 , G11C5/06
摘要： A flash memory device includes: first pads; second pads; third pads; a memory cell array; a row decoder block; a buffer block that stores a command and an address received from an external semiconductor chip through the first pads and provides the address to the row decoder block; a page buffer block that is connected to the memory cell array through bit lines, is connected to the third pads through data lines, and exchanges data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block that receives the command from the buffer block, receives control signals from the external semiconductor chip through the second pads, and controls the row decoder block and the page buffer block based on the received command and the received control signals.
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公开(公告)号：US20240161790A1
公开(公告)日：2024-05-16
申请号：US18203754
申请日：2023-05-31
发明人： Jaehue SHIN , Yongsung CHO , Daeseok BYEON
CPC分类号： G11C7/1057 , G11C5/14 , G11C7/1069 , G11C7/12
摘要： A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected with the memory cells through a plurality of bit lines. A sensing node is connected to a bit line for each buffer circuit. The plurality of page buffer units are respectively connected with sensing nodes, each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wires in the proximity of the sensing node are used to reduce coupling problems caused by a low capacitance of the sensing node.
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公开(公告)号：US20210074717A1
公开(公告)日：2021-03-11
申请号：US16835484
申请日：2020-03-31
发明人： Bongsoon LIM , Daeseok BYEON
IPC分类号： H01L27/11575 , H01L27/11551 , H01L27/11582 , H01L27/11548 , H01L29/04 , H01L27/11519 , H01L27/11565
摘要： Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.
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公开(公告)号：US20210066281A1
公开(公告)日：2021-03-04
申请号：US16944711
申请日：2020-07-31
发明人： Taehong KWON , Youngsun MIN , Daeseok BYEON , Kyunghwa YUN
IPC分类号： H01L25/18 , H01L23/00 , H01L25/065 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/30
摘要： A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.
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公开(公告)号：US20210066276A1
公开(公告)日：2021-03-04
申请号：US16806030
申请日：2020-03-02
发明人： Chanho KIM , Dongku KANG , Daeseok BYEON
摘要： An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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公开(公告)号：US20210065801A1
公开(公告)日：2021-03-04
申请号：US16862167
申请日：2020-04-29
发明人： Taehong KWON , Youngsun MIN , Daeseok BYEON , Kyunghwa YUN
摘要： A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.
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公开(公告)号：US20170110197A1
公开(公告)日：2017-04-20
申请号：US15189136
申请日：2016-06-22
发明人： Hyunkook PARK , Yeongtaek LEE , Daeseok BYEON
CPC分类号： G11C16/28 , G11C5/147 , G11C7/067 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C2013/0054 , H03K5/08 , H03K5/24
摘要： Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.
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公开(公告)号：US20230207549A1
公开(公告)日：2023-06-29
申请号：US18179056
申请日：2023-03-06
发明人： Chanho KIM , Dongku KANG , Daeseok BYEON
CPC分类号： H01L25/18 , H01L23/481 , H01L24/08 , H01L2224/05647 , H01L2224/08145 , H01L24/05
摘要： An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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公开(公告)号：US20220399273A1
公开(公告)日：2022-12-15
申请号：US17721481
申请日：2022-04-15
发明人： Changyeon YU , Pansuk KWAK , Daeseok BYEON
IPC分类号： H01L23/528 , G11C16/08 , H01L27/11582 , H01L27/11573
摘要： A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.
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