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公开(公告)号:US08962422B2
公开(公告)日:2015-02-24
申请号:US13804398
申请日:2013-03-14
发明人: Ho-Jun Seong , Jae-Hwang Sim
IPC分类号: H01L27/088 , H01L29/66 , H01L21/28 , H01L29/788 , H01L27/115 , H01L49/02 , H01L27/06
CPC分类号: H01L29/66477 , H01L21/28273 , H01L27/0629 , H01L27/11521 , H01L28/20 , H01L29/66825 , H01L29/7881
摘要: A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern.
摘要翻译: 一种制造半导体器件的方法包括蚀刻衬底以形成在有源区上限定有源区和下栅极图案的场沟槽,下栅极图案包括隧道绝缘图案和下栅极电极图案,填充场绝缘 在沟槽中形成场区域,在下栅极图案上形成上栅极图案,在场区域和上栅极图案上依次形成停止层和缓冲层,在缓冲层上形成第一电阻图案 并且在上栅极图案上的缓冲层上形成第二电阻图案,形成覆盖第一和第二电阻图案的层间绝缘层,并执行平面化处理以去除层间绝缘层的顶表面,以及 以去除第二电阻图案。