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    Nonvolatile memory device and method of manufacturing the same
    3.
    发明授权
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08829644B2

    公开(公告)日：2014-09-09

    申请号：US14072250

    申请日：2013-11-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jae-Hwang Sim ,  Keon-Soo Kim ,  Kyung-Hoon Min ,  Min-Sung Song ,  Yeon-Wook Jung

    IPC分类号： H01L21/70 ,  H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66

    CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

    摘要： In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

    摘要翻译： 在非易失性存储器件及其制造方法中，器件隔离图案和有源区域在衬底上沿第一方向延伸。 在基板的有源区上形成第一电介质图案。 导电堆叠结构布置在第一电介质图案上，并且在一对相邻的导电堆叠结构之间形成凹部。 保护层形成在堆叠结构的侧壁上，以保护堆叠结构的侧壁不沿着第一方向过度蚀刻。 保护层包括具有氧化物并设置在浮栅电极的侧壁上的防蚀层和控制栅极线的侧壁以及覆盖导电堆叠结构侧壁的间隔层。

    Method of fabricating a semiconductor device and a semiconductor device fabricated by the method
    7.
    发明授权
    Method of fabricating a semiconductor device and a semiconductor device fabricated by the method 有权
    通过该方法制造半导体器件和半导体器件的方法

    公开(公告)号：US09508551B2

    公开(公告)日：2016-11-29

    申请号：US14665141

    申请日：2015-03-23

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hojun Seong ,  Jae-Hwang Sim ,  Jeehoon Han

    IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/033 ,  H01L21/768 ,  H01L27/115 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/311

    CPC分类号： H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines.

    摘要翻译： 制造半导体器件的方法包括在衬底的第一表面上堆叠蚀刻目标层，第一掩模层和第二掩模层。 多个第一间隔线彼此平行地形成，并且形成第二掩模层上的第一间隔垫线。 形成与第二掩模层上的至少第一间隔垫线接触的第三掩模焊盘。 蚀刻第二掩模层和第一掩模层以形成一个或多个第一掩模线，第一掩模预焊垫和第二掩模图案。 分别形成覆盖第一掩模预备焊盘和第一掩模线的侧壁的第二间隔线。 形成第一掩模垫。 蚀刻目标层被蚀刻以形成连接到导线的导电线和导电焊盘。

    Methods of fabricating semiconductor devices including multiple patterning
    8.
    发明授权
    Methods of fabricating semiconductor devices including multiple patterning 有权
    制造包括多个图案化的半导体器件的方法

    公开(公告)号：US09461058B2

    公开(公告)日：2016-10-04

    申请号：US15016737

    申请日：2016-02-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

    IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/788

    CPC分类号： H01L27/11519 ,  H01L21/0214 ,  H01L21/28273 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L27/11524 ,  H01L29/0696 ,  H01L29/6653 ,  H01L29/6656

    摘要： Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

    摘要翻译： 制造半导体器件的方法可以包括在衬底上形成阻挡层，下硬掩模层，中间硬掩模层和上硬掩模图案，在上硬掩模图案的侧壁上形成第一间隔图案，选择性地蚀刻 使用第一间隔图案作为蚀刻掩模的中间硬掩模层，在蚀刻的中间硬掩模层的侧壁上形成第二间隔图案，使用蚀刻的第二间隔层作为蚀刻掩模选择性地蚀刻下硬掩模层，形成图案掩模 露出细胞区域并覆盖蚀刻的下部硬掩模层和阻挡层上的共同源极线区域，并且使用蚀刻的下部硬掩模层和图案化掩模图案作为蚀刻掩模选择性地蚀刻阻挡层以形成阻挡层图案 。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING MULTIPLE PATTERNING
    9.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING MULTIPLE PATTERNING 有权
    制造包含多种图案的半导体器件的方法

    公开(公告)号：US20160233223A1

    公开(公告)日：2016-08-11

    申请号：US15016737

    申请日：2016-02-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Min-Sung SONG ,  Jae-Hwang Sim ,  Joon-Sung Lim

    IPC分类号： H01L27/115 ,  H01L21/311 ,  H01L29/788 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308

    CPC分类号： H01L27/11519 ,  H01L21/0214 ,  H01L21/28273 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L27/11524 ,  H01L29/0696 ,  H01L29/6653 ,  H01L29/6656

    摘要： Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

    摘要翻译： 制造半导体器件的方法可以包括在衬底上形成阻挡层，下硬掩模层，中间硬掩模层和上硬掩模图案，在上硬掩模图案的侧壁上形成第一间隔图案，选择性地蚀刻 使用第一间隔图案作为蚀刻掩模的中间硬掩模层，在蚀刻的中间硬掩模层的侧壁上形成第二间隔图案，使用蚀刻的第二间隔层作为蚀刻掩模选择性地蚀刻下硬掩模层，形成图案掩模 露出细胞区域并覆盖蚀刻的下部硬掩模层和阻挡层上的共同源极线区域，并且使用蚀刻的下部硬掩模层和图案化掩模图案作为蚀刻掩模选择性地蚀刻阻挡层以形成阻挡层图案 。

    Semiconductor memory devices and methods of fabricating the same
    10.
    发明授权
    Semiconductor memory devices and methods of fabricating the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09379123B2

    公开(公告)日：2016-06-28

    申请号：US14848423

    申请日：2015-09-09

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

    IPC分类号： H01L21/764 ,  H01L27/115 ,  H01L29/423

    CPC分类号： H01L27/11524 ,  H01L21/764 ,  H01L29/42324

    摘要： Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

    摘要翻译： 提供一种半导体存储器件及其制造方法。 半导体存储器件可以包括半导体衬底，其具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，设置在第一区域上的栅电极以跨越有源区域， 存储图案，设置在所述栅电极和所述有源区之间，阻挡绝缘层，设置在所述栅电极和所述电荷存储图案之间并在所述第一沟槽上延伸以限定所述第一沟槽中的第一气隙，以及间隔开的绝缘图案 从第二沟槽的底表面到第二沟槽中限定第二气隙。