公开(公告)号：US20230099738A1

公开(公告)日：2023-03-30

申请号：US17872527

申请日：2022-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinook Jung ,  Jaewoo Park ,  Myoungbo Kwak ,  Junghwan Choi

IPC: H03K5/01 ,  H03H11/16

Abstract: A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.