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公开(公告)号：US12063044B2
公开(公告)日：2024-08-13
申请号：US18189599
申请日：2023-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsun Lee , Jaewoo Park , Myoungbo Park , Jinook Jung , Junghwan Choi
CPC classification number: H03L7/093 , H03L7/0818 , H03L7/0991
Abstract: A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.
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公开(公告)号：US20240364351A1
公开(公告)日：2024-10-31
申请号：US18765582
申请日：2024-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsun Lee , Jaewoo Park , Myoungbo Kwak , Jinook Jung , Junghwan Choi
CPC classification number: H03L7/093 , H03L7/0818 , H03L7/0991
Abstract: A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.
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公开(公告)号：US20250060769A1
公开(公告)日：2025-02-20
申请号：US18760350
申请日：2024-07-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhan Choi , Jaewoo Park , Myoungbo Kwak , Jinook Jung
Abstract: An example low dropout (LDO) regulator includes a voltage regulating circuit and an adaptive biasing circuit. The voltage regulating circuit is configured to regulate an output voltage of an output node connected with a load by using the output voltage as first feedback. The adaptive biasing circuit is configured to generate a biasing signal that supports regulation of the output voltage by using a sensing signal in an internal node of the voltage regulating circuit as second feedback, and to provide the biasing signal to the voltage regulating circuit.
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公开(公告)号：US11940830B2
公开(公告)日：2024-03-26
申请号：US17709853
申请日：2022-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinook Jung , Jaewoo Park , Junhan Choi , Myoungbo Kwak , Junghwan Choi
IPC: G11C11/4074 , G05F1/575 , G11C11/4076 , G11C11/4093
CPC classification number: G05F1/575 , G11C11/4074 , G11C11/4076 , G11C11/4093
Abstract: Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.
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Patent Agency Ranking
公开(公告)号：US11888486B2
公开(公告)日：2024-01-30
申请号：US17872527
申请日：2022-07-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinook Jung , Jaewoo Park , Myoungbo Kwak , Junghwan Choi
CPC classification number: H03K5/01 , H03H11/16 , H03K2005/00019
Abstract: A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.
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公开(公告)号：US20230099738A1
公开(公告)日：2023-03-30
申请号：US17872527
申请日：2022-07-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinook Jung , Jaewoo Park , Myoungbo Kwak , Junghwan Choi
Abstract: A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.
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公开(公告)号：US20250167790A1
公开(公告)日：2025-05-22
申请号：US18889081
申请日：2024-09-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsun Lee , Suneui Park , Jaewoo Park , Jinook Jung , Myoungbo Kwak
Abstract: An example apparatus for generating a clock includes a phase locked loop circuit to generate a first clock signal having a specified frequency through an oscillator, a monitoring circuit to monitor a first bit error rate (BER) of a first signal received in response to the first clock signal, and a control logic circuit to control the phase locked loop circuit based on a monitoring result. The control logic circuit is to connect a first boosting current source, which is included in the phase locked loop circuit, with the oscillator, when the first bit error rate is equal to or greater than a preset threshold value, and disconnect a second boosting current source, which is previously connected with the oscillator, from the oscillator, when the first bit error rate is less than the threshold value.
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公开(公告)号：US20250060771A1
公开(公告)日：2025-02-20
申请号：US18806082
申请日：2024-08-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhan Choi , Jaewoo Park , Myoungbo Kwak , Jinook Jung
Abstract: Provided are a low dropout (LDO) regulator controlling operation biasing of a transistor connected to an output node to have a wide bandwidth and provide a stable voltage at a fast speed, and a memory device including the LDO regulator. The LDO regulator includes a first low voltage transistor in which a first terminal thereof is connected to an output node configured to provide an output voltage to a load and a second terminal thereof is connected to a first node, an operational amplifier configured to compare a reference voltage with the output voltage and output the comparison result to a gate terminal of a first low voltage transistor, and an operation biasing control circuit connected to the output node and the first node, and including at least one high voltage transistor.
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公开(公告)号：US20240056084A1
公开(公告)日：2024-02-15
申请号：US18189599
申请日：2023-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsun Lee , Jaewoo Park , Myoungbo Kwak , Jinook Jung , Junghwan Choi
CPC classification number: H03L7/093 , H03L7/0991 , H03L7/0818
Abstract: A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.
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