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公开(公告)号：US20250036520A1
公开(公告)日：2025-01-30
申请号：US18420877
申请日：2024-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinsoo Lim , Changkyu Seol , Myoungbo Kwak , Daewook Kim , Dongjin Park , Hyoungbae Ahn , Youngdon Choi , Junghwan Choi
IPC: G06F11/10
Abstract: An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.
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公开(公告)号：US12052032B2
公开(公告)日：2024-07-30
申请号：US18055867
申请日：2022-11-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinsoo Lim , Changkyu Seol , Myoungbo Kwak , Pilsang Yoon
CPC classification number: H03M13/09 , H03M13/1125 , H03M13/45
Abstract: Disclosed is an electronic device, which includes an ECC decoder that performs ECC decoding on a flit including a plurality of PAM-4 symbols for each of a plurality of ECC groups, a CRC decoder that performs CRC decoding on the ECC decoded flit to obtain data, and an erasure decoding unit that calculates an LLR for each of the PAM-4 symbols when the CRC decoding fails, extracts an error symbol candidate from among the plurality of PAM-4 symbols for each of the plurality of ECC groups based on the LLR, and performs the ECC decoding again after erasing the error symbol candidate.
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公开(公告)号：US20240178863A1
公开(公告)日：2024-05-30
申请号：US18511740
申请日：2023-11-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinsoo Lim , Changkyu Seol , Myoungbo Kwak , Daewook Kim , Dongjin Park , Youngdon Choi
CPC classification number: H03M13/1595 , H03M13/2778 , H03M13/2927
Abstract: A device includes a receiver configured to receive a plurality of Error Correction Code (ECC) codewords transmitted from an external device through a channel including one or more lanes; an ECC decoder configured to generate a plurality of post ECC codewords by performing error correction with respect to the plurality of ECC codewords and generating a first cyclic redundancy check (CRC) codeword based on the plurality of post ECC codewords; a CRC checker configured to determine whether an error exists in the first CRC codeword; and a post ECC decoder configured to, when it is determined that the error exists in the first CRC codeword, generate a second CRC codeword by estimating a remaining error position based on error correction result information received from the ECC decoder and performing remaining error correction with respect to the plurality of post ECC codewords based on the remaining error position.
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公开(公告)号：US20240176385A1
公开(公告)日：2024-05-30
申请号：US18363906
申请日：2023-08-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junyoung Maeng , Jaewoo Park , Myoungbo Kwak , Junghwan Choi
IPC: G06F1/10
CPC classification number: G06F1/10
Abstract: An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.
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公开(公告)号：US20230396268A1
公开(公告)日：2023-12-07
申请号：US18055867
申请日：2022-11-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinsoo Lim , Changkyu Seol , Myoungbo Kwak , Pilsang Yoon
CPC classification number: H03M13/09 , H03M13/1125 , H03M13/45
Abstract: Disclosed is an electronic device, which includes an ECC decoder that performs ECC decoding on a flit including a plurality of PAM-4 symbols for each of a plurality of ECC groups, a CRC decoder that performs CRC decoding on the ECC decoded flit to obtain data, and an erasure decoding unit that calculates an LLR for each of the PAM-4 symbols when the CRC decoding fails, extracts an error symbol candidate from among the plurality of PAM-4 symbols for each of the plurality of ECC groups based on the LLR, and performs the ECC decoding again after erasing the error symbol candidate.
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Patent Agency Ranking
公开(公告)号：US20250167790A1
公开(公告)日：2025-05-22
申请号：US18889081
申请日：2024-09-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsun Lee , Suneui Park , Jaewoo Park , Jinook Jung , Myoungbo Kwak
Abstract: An example apparatus for generating a clock includes a phase locked loop circuit to generate a first clock signal having a specified frequency through an oscillator, a monitoring circuit to monitor a first bit error rate (BER) of a first signal received in response to the first clock signal, and a control logic circuit to control the phase locked loop circuit based on a monitoring result. The control logic circuit is to connect a first boosting current source, which is included in the phase locked loop circuit, with the oscillator, when the first bit error rate is equal to or greater than a preset threshold value, and disconnect a second boosting current source, which is previously connected with the oscillator, from the oscillator, when the first bit error rate is less than the threshold value.
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公开(公告)号：US20250060771A1
公开(公告)日：2025-02-20
申请号：US18806082
申请日：2024-08-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhan Choi , Jaewoo Park , Myoungbo Kwak , Jinook Jung
Abstract: Provided are a low dropout (LDO) regulator controlling operation biasing of a transistor connected to an output node to have a wide bandwidth and provide a stable voltage at a fast speed, and a memory device including the LDO regulator. The LDO regulator includes a first low voltage transistor in which a first terminal thereof is connected to an output node configured to provide an output voltage to a load and a second terminal thereof is connected to a first node, an operational amplifier configured to compare a reference voltage with the output voltage and output the comparison result to a gate terminal of a first low voltage transistor, and an operation biasing control circuit connected to the output node and the first node, and including at least one high voltage transistor.
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公开(公告)号：US20240406041A1
公开(公告)日：2024-12-05
申请号：US18422058
申请日：2024-01-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Young Choi , Jaeha Kim , Meyong Su Ko , Myoungbo Kwak , Jaewoo Park , Youngdon Choi , Junghwan Choi
IPC: H04L25/06 , H04L1/1867
Abstract: A receiver for receiving a data signal, comprising, an analog-to-digital converter configured to convert the data signal into digital data, a first-in-first-out buffer configured to determine a frame boundary of the digital data by referring to a comma index to output the digital data in units of data frames according to the determined frame boundary, a decision feedback equalizer configured to process a data frame output from the first-in-first-out buffer through a decision feedback equalization operation, wherein feedback data used in the decision feedback equalization operation of the data frame uses a predetermined fixed pattern, and a comma detector configured to generate the comma index by comparing a determined value of the data frame with the predetermined fixed pattern. The data frame may include a preceding data field in which a message is stored and a subsequent comma field having the same bit value as the fixed pattern.
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公开(公告)号：US20240056084A1
公开(公告)日：2024-02-15
申请号：US18189599
申请日：2023-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsun Lee , Jaewoo Park , Myoungbo Kwak , Jinook Jung , Junghwan Choi
CPC classification number: H03L7/093 , H03L7/0991 , H03L7/0818
Abstract: A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.
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10.发明公开公开(公告)号：US20230291412A1
公开(公告)日：2023-09-14
申请号：US17974703
申请日：2022-10-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyoungjun Roh , Jaewoo Park , Myoungbo Kwak , Jejoong Woo , Junghwan Choi
Abstract: An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.
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