公开(公告)号：US20220284299A1

公开(公告)日：2022-09-08

申请号：US17398296

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd. ,  Ulsan National Institute of Science and Technology

Inventor： Sehwan LEE ,  Hyeon Uk SIM ,  Jongeun LEE

IPC: G06N3/08 ,  G06N3/04 ,  G06K9/62

Abstract: A processor-implemented neural network operation method includes: receiving a first activation gradient and a first threshold corresponding to a layer included in a neural network; sparsifying the first activation gradient based on the first threshold; determining a second activation gradient by performing a neural network operation based on the sparsified first activation gradient; determining a second threshold by updating the first threshold based on the second activation gradient; and performing a neural network operation based on the second activation gradient and the second threshold.

公开(公告)号：US20220269930A1

公开(公告)日：2022-08-25

申请号：US17369036

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Sehwan LEE ,  Jongeun LEE ,  Jooyeon CHOI

IPC: G06N3/063

Abstract: A neural network operation apparatus includes an input register to store an input feature map, a processing element array including a processing element to perform an operation based on the input feature map and a weight matrix, and a controller to map a portion of the input feature map and a portion of the weight matrix, both on which the operation is to be performed, to the processing element.

公开(公告)号：US20220253692A1

公开(公告)日：2022-08-11

申请号：US17400353

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongseok YU ,  Yoojin KIM ,  Seongwook PARK ,  Hyun Sun PARK ,  Sehwan LEE ,  Jun-Woo JANG ,  Deokjin JOO

IPC: G06N3/08 ,  G06F9/30 ,  G06F7/02

Abstract: Disclosed is a method and apparatus of operating a neural network. The neural network operation method includes receiving data for the neural network operation, verifying whether competition occurs between a first data traversal path corresponding to a first operation device and a second data traversal path corresponding to a second operation device, determining first operand data and second operand data from among the data using a result of the verifying and a priority between the first data traversal path and the second data traversal path, and performing the neural network operation based on the first operand data and the second operand data.

公开(公告)号：US20220180187A1

公开(公告)日：2022-06-09

申请号：US17307072

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongyoung KIM ,  Sehwan LEE

IPC: G06N3/08 ,  G06F17/16 ,  G06F9/30

Abstract: A method and apparatus for performing deep learning operations. A computation apparatus includes an adder tree-based tensor core configured to perform a tensor operation, and a multiplier and accumulator (MAC)-based vector core configured to perform a vector operation using an output of the tensor core as an input.

公开(公告)号：US20210357734A1

公开(公告)日：2021-11-18

申请号：US17239892

申请日：2021-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gopinath Vasanth MAHALE ,  Pramod Parameshwara UDUPA ,  Kiran Kolar CHANDRASEK HARAN ,  Sehwan LEE

IPC: G06N3/063

Abstract: A z-first reference neural processing unit (NPU) for mapping Winograd Convolution is disclosed where the NPU includes memory banks configured to store input feature maps (IFMs) in a z-first data storage layout, each of the memory banks being configured to store the IFMs in one of a direct convolution (DConv) mode or a Winograd convolution (WgConv) mode, a reconfigurable IFM distributor configured to receive the IFMs from the memory banks, a parallel reconfigurable Winograd forward transform module configured to receive the IFMs from the reconfigurable IFM distributor and to transform the IFMs in a Winograd domain to transformed IFMs in the WgConv mode, multiply and accumulate (MAC) units configured to perform dot product operations on one of IFMs in the DConv mode and the transformed IFMs in the WgConv mode to obtain intermediate output feature maps (OFMs), and a reconfigurable OFM adder and Winograd inverse transform module configured to generate one of an OFM from the intermediate OFMs in the DConv mode and OFMs from the intermediate OFMs in the WgConv.

公开(公告)号：US20210117791A1

公开(公告)日：2021-04-22

申请号：US17112041

申请日：2020-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonho SONG ,  Sehwan LEE ,  Junwoo JANG

IPC: G06N3/08 ,  G06N3/04

Abstract: A neural network apparatus configured to perform a deconvolution operation includes a memory configured to store a first kernel; and a processor configured to: obtain, from the memory, the first kernel; calculate a second kernel by adjusting an arrangement of matrix elements comprised in the first kernel; generate sub-kernels by dividing the second kernel; perform a convolution operation between an input feature map and the sub-kernels using a convolution operator; and generate an output feature map, as a deconvolution of the input feature map, by merging results of the convolution operation.

公开(公告)号：US20200285887A1

公开(公告)日：2020-09-10

申请号：US16884232

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Sehwan LEE ,  Leesup KIM ,  Hyeonuk KIM ,  Jaehyeong SIM ,  Yeongjae CHOI

IPC: G06K9/62 ,  G06N3/04 ,  G06N3/063

Abstract: A processor-implemented neural network method includes: obtaining, from a memory, data of an input feature map and kernels having a binary-weight, wherein the kernels are to be processed in a layer of a neural network; decomposing each of the kernels into a first type sub-kernel reconstructed with weights of a same sign, and a second type sub-kernel for correcting a difference between a respective kernel, among the kernels, and the first type sub-kernel; performing a convolution operation by using the input feature map and the first type sub-kernels and the second type sub-kernels decomposed from each of the kernels; and obtaining an output feature map by combining results of the convolution operation.

公开(公告)号：US20200218936A1

公开(公告)日：2020-07-09

申请号：US16733314

申请日：2020-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： DINESH KUMAR YADAV ,  ANKUR DESHWAL ,  SAPTARSI DAS ,  Junwoo JANG ,  Sehwan LEE

IPC: G06K9/62 ,  G06T1/00 ,  G06N3/08

Abstract: A method of performing convolution in a neural network with variable dilation rate is provided. The method includes receiving a size of a first kernel and a dilation rate, determining at least one of size of one or more disintegrated kernels based on the size of the first kernel, a baseline architecture of a memory and the dilation rate, determining an address of one or more blocks of an input image based on the dilation rate, and one or more parameters associated with a size of the input image and the memory. Thereafter, the one or more blocks of the input image and the one or more disintegrated kernels are fetched from the memory, and an output image is obtained based on convolution of each of the one or more disintegrated kernels and the one or more blocks of the input image.

公开(公告)号：US20190138891A1

公开(公告)日：2019-05-09

申请号：US16106902

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namjoon KIM ,  Sehwan LEE ,  Junwoo JANG

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A neural network apparatus includes a plurality of node buffers connected to a node lane and configured to store input node data by a predetermined bit size; a plurality of weight buffers connected to a weight lane and configured to store weights; and one or more processors configured to: generate first and second split data by splitting the input node data by the predetermined bit size, store the first and second split data in the node buffers, output the first split data to an operation circuit for a neural network operation on an index-by-index basis, shift the second split data, and output the second split data to the operation circuit on the index-by-index basis.