公开(公告)号：US09711192B2

公开(公告)日：2017-07-18

申请号：US14931291

申请日：2015-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Tae-Young Oh ,  Seong-Jin Jang

IPC: G11C5/14 ,  G11C7/10 ,  G11C8/12

CPC classification number: G11C5/147 ,  G11C5/148 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/12 ,  G11C2207/2227

Abstract: A memory device that operates in a low-power operation mode includes a memory cell array, a page size changing circuit, and an encoding and decoding changing circuit. The page size changing circuit changes the number of data items prefetched in the memory cell array according to a power mode during a read operation. The encoding and decoding changing circuit changes a level of data written in the memory cell array according to the power mode during a read operation.