公开(公告)号：US06407422B1

公开(公告)日：2002-06-18

申请号：US09556571

申请日：2000-04-24

申请人： Katsuaki Asano ,  Yasuyuki Ito ,  Shun Mitarai ,  Akihiko Ochiai

发明人： Katsuaki Asano ,  Yasuyuki Ito ,  Shun Mitarai ,  Akihiko Ochiai

IPC分类号： H01L27108

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55

摘要： Provided is a semiconductor memory device in which defective contact, deterioration in transistor characteristics and other problems are solved with a thermally stable, conductive diffusion barrier layer against oxygen, and against constituent elements in a plug material and a lower electrode, formed at the interface between a plug and the lower electrode made of a noble metal. The semiconductor memory device comprises a dielectric capacitor of a stacked structure including a first electrode (a lower electrode), a dielectric film and a second electrode (an upper electrode) and a conductive plug connected to the lower electrode, wherein the lower electrode connected to the conductive plug includes a metal suboxide layer with conductiveness and a diffusion barrier layer blocking diffusion of oxygen, and the metal suboxide layer and the diffusion barrier layer are stacked in the order from the conductive plug side of the lower electrode.

摘要翻译： 提供了一种半导体存储器件，其中通过针对氧的热稳定的导电扩散阻挡层以及针对形成在插塞材料和下电极之间的界面处的构成元件来解决不良接触，晶体管特性劣化和其他问题 插头和由贵金属制成的下电极。 半导体存储器件包括具有第一电极（下电极），电介质膜和第二电极（上电极）和连接到下电极的导电插塞的堆叠结构的介质电容器，其中下电极连接到 导电插塞包括具有导电性的金属低氧化物层和阻挡氧的扩散的扩散阻挡层，并且金属低氧化物层和扩散阻挡层以下电极的导电插塞侧的顺序层叠。