公开(公告)号：US06530380B1

公开(公告)日：2003-03-11

申请号：US09443428

申请日：1999-11-19

申请人： Mei Sheng Zhou ,  Vincent Sih ,  Simon Chooi ,  Zainab Bte Ismail ,  Ping Yu Ee ,  Sang Yee Loong

发明人： Mei Sheng Zhou ,  Vincent Sih ,  Simon Chooi ,  Zainab Bte Ismail ,  Ping Yu Ee ,  Sang Yee Loong

IPC分类号： H01L21302

CPC分类号： H01L21/31116

摘要： A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may be fabricated, with improved properties and with attenuated degradation. There is first provided a substrate with employed within a microelectronics fabrication having formed thereon patterned microelectronics layers with closely spaced features. There is then formed a salicide block layer employing silicon oxide dielectric material which may be selectively doped. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the patterned photoresist etch mask layer employing dry plasma reactive ion etching. An anhydrous etching environment is then employed to completely remove the silicon oxide dielectric salicide block layer with attenuated degradation of the microelectronics fabrication.

摘要翻译： 用于完全去除在微电子制造中使用的衬底上选择性地形成的介电层的方法，其中可以制造具有改进的性质和衰减劣化的紧密间隔的结构例如自对准金属硅化物（或自对准硅））电接触的区域。 首先提供了在微电子制造中使用的衬底，其中形成有具有紧密间隔的特征的图案化微电子层。 然后形成可以选择性掺杂的氧化硅介电材料的自对准硅化物阻挡层。 然后在衬底上形成图案化的光致抗蚀剂蚀刻掩模层。 然后使用干等离子体反应离子蚀刻蚀刻图案化的光致抗蚀剂蚀刻掩模层的图案。 然后使用无水蚀刻环境以完全去除具有微电子制造的衰减的氧化硅介电硅化物阻挡层。