公开(公告)号：US20230367599A1

公开(公告)日：2023-11-16

申请号：US18141466

申请日：2023-04-30

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F9/30

CPC classification number: G06F9/30141 ,  G06F9/30094

Abstract: Systems and methods are disclosed for vector gather with a narrow datapath. For example, some methods may include reading b bits of a vector of indices into a first operand buffer; reading b bits of the vector of source data into a second operand buffer, including an element indexed by a first index stored in the first operand buffer; checking whether other indices stored in the first operand buffer point to elements of the vector of source data stored in the second operand buffer; during a single clock cycle, copying a plurality of elements stored in the second operand buffer that are pointed to by indices stored in the first operand buffer to a third operand buffer; and updating flags in a completion flags buffer corresponding to those indices to indicate that handling of those indices has completed.

公开(公告)号：US20230305969A1

公开(公告)日：2023-09-28

申请号：US18024208

申请日：2021-09-01

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F12/14 ,  G06F9/30 ,  G06F21/62

CPC classification number: G06F12/1458 ,  G06F9/30036 ,  G06F21/6218 ,  G06F2212/1052

Abstract: Systems and methods are disclosed for memory protection for memory protection for gather-scatter operations. For example, an integrated circuit may include a processor core; a memory protection circuit configured to check for memory protection violations with a protection granule; and an index range circuit configured to: memoize a maximum value and a minimum value of a tuple of indices stored in a vector register of the processor core as the tuple of indices is written to the vector register; determine a range of addresses for a gather-scatter memory instruction that takes the vector register as a set of indices based on a base address of a vector in memory, the memoized minimum value, and the memoized maximum value; and check, using the memory protection circuit during a single clock cycle, whether accessing elements of the vector within the range of addresses will cause a memory protection violation.

公开(公告)号：US20220292183A1

公开(公告)日：2022-09-15

申请号：US17826622

申请日：2022-05-27

Applicant: SiFive, Inc.

Inventor： Alex Solomatnikov ,  Krste Asanovic ,  Yann Loisel ,  Cyril Bresch

IPC: G06F21/52

Abstract: Systems and methods are disclosed for secure control flow prediction. Some implementations may be used to eliminate or mitigate the Spectre-class of attacks in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions may include a control flow predictor with entries that include branch target addresses associated with instructions. The branch target addresses may be predictions. A context tag associated with an entry may be compared to a context identifier associated with a currently executing process. Responsive to a mismatch between the context tag and the context identifier, the control flow predictor may provide an alternate value in place of a branch target address.

公开(公告)号：US11301251B2

公开(公告)日：2022-04-12

申请号：US16856462

申请日：2020-04-23

Applicant: SiFive, Inc.

Inventor： Joshua Smith ,  Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

Abstract: Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.

公开(公告)号：US20220083340A1

公开(公告)日：2022-03-17

申请号：US17418933

申请日：2019-12-12

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.

公开(公告)号：US10996952B2

公开(公告)日：2021-05-04

申请号：US16215328

申请日：2018-12-10

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.

公开(公告)号：US20200210189A1

公开(公告)日：2020-07-02

申请号：US16553839

申请日：2019-08-28

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F12/0875

Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.