公开(公告)号：US20150294938A1

公开(公告)日：2015-10-15

申请号：US14669527

申请日：2015-03-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi ,  Mu-Hsuan Chan

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.

Abstract translation: 提供了一种用于制造导电通孔结构的方法，其包括以下步骤：在密封剂中形成贯穿其中的多个开口; 在密封剂和密封剂的开口中形成介电层; 在密封剂的开口中的电介质层中形成多个通孔; 以及在通路中形成导电材料，从而形成导电通路。 因此，通过用具有电介质层的具有粗糙壁面的开口填充以形成具有均匀的壁表面的通孔，本发明提高了导电通孔的质量。

公开(公告)号：US20140342505A1

公开(公告)日：2014-11-20

申请号：US14151153

申请日：2014-01-09

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi ,  Yan-Yi Liao

IPC: H01L21/52 ,  H01L21/78

CPC classification number: H01L21/52 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：提供载体; 在载体上设置至少一个半导体元件; 在所述载体和所述半导体元件上形成用于封装所述半导体元件的密封剂; 移除载体; 将压力构件设置在密封剂上; 以及在半导体元件和密封剂上形成RDL结构，由此抑制通过压力构件的内部应力，从而减轻密封剂边缘的翘曲。