公开(公告)号：US08699291B1

公开(公告)日：2014-04-15

申请号：US13415052

申请日：2012-03-08

申请人： Chin Ghee Ch'ng ,  Wei Yee Koay ,  Boon Jin Ang

发明人： Chin Ghee Ch'ng ,  Wei Yee Koay ,  Boon Jin Ang

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/148

摘要： Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.

摘要翻译： 公开了用于操作存储器电路的电路和技术。 所公开的电路包括存储器电路和具有耦合到存储器电路的输出端的睡眠电路。 睡眠电路可操作以接收控制信号并进一步可操作以将存储器电路放置在不同的操作模式中。 存储器电路可以至少部分地基于控制信号放置在第一操作模式，第二操作模式或第三操作模式中。 休眠电路的输入端子耦合到控制电路的输出端子。 控制电路可操作以接收使能信号，并且可操作以分别基于使能信号和第一，第二和第三电压电平在第一，第二和第三工作模式下将控制信号提供给第一，第二和第三电压电平， 时钟信号。

公开(公告)号：US07479803B1

公开(公告)日：2009-01-20

申请号：US10960302

申请日：2004-10-06

申请人： Darren van Wageningen ,  Boon Jin Ang

发明人： Darren van Wageningen ,  Boon Jin Ang

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： G01R31/31705

摘要： Techniques are provided to hardware debug a programmable logic integrated circuit that includes a hardware intellectual property block (HIP). The HIP includes a logic circuit and state machine(s). The state machine outputs state machine information depending on selected signals within the logic circuit. The HIP block can also output data from a number of internal registers/flip-flops. Optional data registering logic can capture the state machine information and output it to a data bus.

摘要翻译： 技术提供给硬件调试包括硬件知识产权块（HIP）的可编程逻辑集成电路。 HIP包括逻辑电路和状态机。 状态机根据逻辑电路内的选定信号输出状态机信息。 HIP块还可以从多个内部寄存器/触发器输出数据。 可选数据注册逻辑可以捕获状态机信息并将其输出到数据总线。

公开(公告)号：US07265587B1

公开(公告)日：2007-09-04

申请号：US11189348

申请日：2005-07-26

申请人： Bee Yee Ng ,  Choong Kit Wong ,  Boon Jin Ang

发明人： Bee Yee Ng ,  Choong Kit Wong ,  Boon Jin Ang

IPC分类号： H03K19/0175

CPC分类号： H03K19/018585 ,  H03K19/01721 ,  H04L25/0264 ,  H04L25/0286

摘要： Methods and apparatus are provided for performing pre-emphasis of signals using buffer circuitry that is not dedicated to LVDS transmission. In an embodiment of the invention, pre-emphasis circuitry is provided to enable unused transistors of the buffer circuitry to increase the current that can be driven onto output signal lines, resulting in sharper signal transitions and improved signal integrity. In addition, circuitry can be provided that limits the duration of the pre-emphasis to a selected period of time, thereby conserving power and limiting the differential voltage between a given pair of transmitted signals.

摘要翻译： 提供的方法和装置用于使用不专用于LVDS传输的缓冲电路来执行信号的预加重。 在本发明的一个实施例中，提供预加重电路以使得缓冲电路的未使用的晶体管能够增加可驱动到输出信号线上的电流，从而产生更清晰的信号转换和改进的信号完整性。 此外，可以提供将预加重的持续时间限制到所选择的时间段的电路，从而节省功率并限制给定的一对发送信号之间的差分电压。