公开(公告)号：US20180038913A1

公开(公告)日：2018-02-08

申请号：US15788292

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Kushal D Murthy ,  Manish Parmar ,  Preetam Tadeparthy ,  Muthusubramanian Venkateswaran

IPC: G01R31/3177 ,  H03K19/0948 ,  G01R31/317 ,  H01L21/66 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2884 ,  G01R31/31723 ,  H01L22/14 ,  H01L22/34 ,  H03K19/0948

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

公开(公告)号：US09823306B2

公开(公告)日：2017-11-21

申请号：US15042132

申请日：2016-02-11

Applicant: Texas Instruments Incorporated

Inventor： Kushal D Murthy ,  Manish Parmar ,  Preetam Tadeparthy ,  Muthusubramanian Venkateswaran

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  H03K19/0948 ,  H01L21/66

CPC classification number: G01R31/3177 ,  G01R31/2884 ,  G01R31/31723 ,  H01L22/14 ,  H01L22/34 ,  H03K19/0948

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.