公开(公告)号：US10784829B2

公开(公告)日：2020-09-22

申请号：US16222849

申请日：2018-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dattatreya Baragur Suryanarayana ,  Kushal D Murthy

IPC: H03F1/52 ,  H03F3/45

Abstract: A circuit includes a power transistor including a first control input and first and second current terminals, the second current terminal to be coupled to a load to provide current to the load. A second transistor includes a second control input and third and fourth current terminals, and the first and second control inputs connected together and the first and third current terminals connected together. A third transistor includes a third control input and fifth and sixth current terminals. A fourth transistor includes a fourth control input and seventh and eighth current terminals, and the seventh current terminal is coupled to the fourth and fifth current terminals. An amplifier amplifies a difference between voltages on the second and fourth current terminals. An output of the amplifier is coupled to the third control input and a diode device is connected between the third and fourth control inputs.

公开(公告)号：US10459030B2

公开(公告)日：2019-10-29

申请号：US15788292

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Kushal D Murthy ,  Manish Parmar ,  Preetam Tadeparthy ,  Muthusubramanian Venkateswaran

IPC: G01R31/00 ,  G01R31/3177 ,  G01R31/28 ,  H03K19/0948 ,  H01L21/66 ,  G01R31/317

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either directly or via the buffer to the first external pin of the IC in order to calibrate the buffer.

公开(公告)号：US20180038913A1

公开(公告)日：2018-02-08

申请号：US15788292

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Kushal D Murthy ,  Manish Parmar ,  Preetam Tadeparthy ,  Muthusubramanian Venkateswaran

IPC: G01R31/3177 ,  H03K19/0948 ,  G01R31/317 ,  H01L21/66 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2884 ,  G01R31/31723 ,  H01L22/14 ,  H01L22/34 ,  H03K19/0948

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

公开(公告)号：US09823306B2

公开(公告)日：2017-11-21

申请号：US15042132

申请日：2016-02-11

Applicant: Texas Instruments Incorporated

Inventor： Kushal D Murthy ,  Manish Parmar ,  Preetam Tadeparthy ,  Muthusubramanian Venkateswaran

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  H03K19/0948 ,  H01L21/66

CPC classification number: G01R31/3177 ,  G01R31/2884 ,  G01R31/31723 ,  H01L22/14 ,  H01L22/34 ,  H03K19/0948

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.