公开(公告)号：US09935121B2

公开(公告)日：2018-04-03

申请号：US15063887

申请日：2016-03-08

Applicant: Toshiba Memory Corporation

Inventor： Satoshi Konagai ,  Yoshihiro Akutsu ,  Masaru Kito

IPC: H01L29/792 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/76879 ,  H01L27/11565

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction. The semiconductor pillar extends in the stacked body in the first direction. The memory film provides between the stacked body and the semiconductor pillar. The conductive member includes a contact and an interconnect. The contact includes metal, the contact extending in the stacked body in the first direction. The interconnect extends in a second direction crossing the first direction, and the interconnect including metal.

公开(公告)号：US09893079B2

公开(公告)日：2018-02-13

申请号：US14834636

申请日：2015-08-25

Applicant: Toshiba Memory Corporation

Inventor： Takeshi Sonehara ,  Masaru Kito

IPC: H01L29/66 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11575

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are stacked on a substrate. The semiconductor layer has one end connected to the substrate, has as its longer direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. Assuming at least one control gate electrode positioned in a lowermost layer of the plurality of control gate electrodes to be a first control gate electrode, the first control gate electrode comprises: a first portion; a second portion adjacent to the first portion; and a third portion connected to the first portion and the second portion.