公开(公告)号：US20150121329A1

公开(公告)日：2015-04-30

申请号：US14068064

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Min FU ,  Yung-Fong LU ,  Chung-Hsing WANG

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout.

Abstract translation: 一种方法包括提供包括表示电路元件的多个单元的半导体器件的第一布局，以及在处理器中提供包括多个单元的单元库。 电路元件包括多个鳍式场效应晶体管（Fin-FET）。 单元库中的多个单元格中的每个单元都显示有指示相应的翅片高度的分别不同的标记。 该方法还包括通过在第一布局中的相应位置放置或替换来自单元库的至少一个单元来产生要制造的半导体器件的第二布局。 来自电池库的至少一个电池包括在第二布局中具有与相邻Fin-FET不同的散热片高度的Fin-FET。