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    SYSTEMS AND METHODS FOR CONTEXT AWARE CIRCUIT DESIGN
    1.
    发明申请
    SYSTEMS AND METHODS FOR CONTEXT AWARE CIRCUIT DESIGN 有权

    公开(公告)号：US20250086371A1

    公开(公告)日：2025-03-13

    申请号：US18961133

    申请日：2024-11-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Chung HSU ,  Yen-Pin CHEN ,  Sung-Yen YEH ,  Jerry Chang-Jui KAO ,  Chung-Hsing WANG

    IPC: G06F30/392 ,  G06F30/367 ,  G06F113/18 ,  G06F119/06

    Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

    SYSTEMS AND METHODS FOR CONTEXT AWARE CIRCUIT DESIGN
    2.
    发明公开
    SYSTEMS AND METHODS FOR CONTEXT AWARE CIRCUIT DESIGN 审中-公开

    公开(公告)号：US20230401369A1

    公开(公告)日：2023-12-14

    申请号：US18232742

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Chung HSU ,  Yen-Pin CHEN ,  Sung-Yen YEH ,  Jerry Chang-Jui KAO ,  Chung-Hsing WANG

    IPC: G06F30/392 ,  G06F30/367

    CPC classification number: G06F30/392 ,  G06F30/367 ,  G06F2119/06

    Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

    LAYOUT MODIFICATION METHOD AND SYSTEM
    5.
    发明申请
    LAYOUT MODIFICATION METHOD AND SYSTEM 审中-公开
    布局修改方法和系统

    公开(公告)号：US20150363540A1

    公开(公告)日：2015-12-17

    申请号：US14833260

    申请日：2015-08-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Xiang LEE ,  Li-Chung HSU ,  Shih-Hsien YANG ,  Ho Che YU ,  King-Ho TAM ,  Chung-Hsing WANG

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/02 ,  G06F2217/78 ,  G06F2217/84

    Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

    Abstract translation: 一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模， 该IC满足第一规格值。 计算机识别IC布局中的多个第一设备的正确子集，使得经修改的IC布局中的第二设备的第一设备的适当子集的替换满足与第一规范值不同的第二规范值。 至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造 一个IC根据修订的IC布局。

    LAYOUT MODIFICATION METHOD AND SYSTEM
    6.
    发明申请
    LAYOUT MODIFICATION METHOD AND SYSTEM 审中-公开
    布局修改方法和系统

    公开(公告)号：US20140351784A1

    公开(公告)日：2014-11-27

    申请号：US14449211

    申请日：2014-08-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Xiang LEE ,  Li-Chung HSU ,  Shih-Hsien YANG ,  Ho Che YU ,  King-Ho TAM ,  Chung-Hsing WANG

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/02 ,  G06F2217/78 ,  G06F2217/84

    Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

    Abstract translation: 一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模， 该IC满足第一规格值。 计算机识别IC布局中的多个第一设备的正确子集，使得经修订的IC布局中的第二设备对第一设备的正确子集的替换满足与第一规范值不同的第二规范值。 至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造 一个IC根据修订的IC布局。

    METHOD AND SYSTEM FOR REPLACING A PATTERN IN A LAYOUT
    7.
    发明申请
    METHOD AND SYSTEM FOR REPLACING A PATTERN IN A LAYOUT 有权
    用于在布局中替换图案的方法和系统

    公开(公告)号：US20140059504A1

    公开(公告)日：2014-02-27

    申请号：US14068006

    申请日：2013-10-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu CHEN ,  Yuan-Te HOU ,  Chung-Min FU ,  Chung-Hsing WANG ,  Wen-Hao CHEN ,  Yi-Kan CHENG

    IPC: G06F17/50

    CPC classification number: G06F17/5077

    Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

    Abstract translation: 接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案 被包括在第二个光掩模中。 所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。 除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。 生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。 输出表示剩余的第一图案和替换图案的数据。

    CIRCUIT TESTING AND MANUFACTURE USING MULTIPLE TIMING LIBRARIES
    10.
    发明申请
    CIRCUIT TESTING AND MANUFACTURE USING MULTIPLE TIMING LIBRARIES 有权

    公开(公告)号：US20210232743A1

    公开(公告)日：2021-07-29

    申请号：US17227748

    申请日：2021-04-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ravi Babu PITTU ,  Chung-Hsing WANG ,  Sung-Yen YEH ,  Li Chung HSU

    IPC: G06F30/3312 ,  G06F30/39 ,  G06F30/367

    Abstract: A method and system for manufacturing a circuit is disclosed. In some embodiments, the system includes: at least one processor configured to: generate a first timing library for a first set of circuit elements for a first set of input parameters based on device characteristics for each of the circuit elements in the first set of circuit elements, and storing the determined device characteristics in a database; and generating a second timing library for a second set of circuit elements for a second set of input parameters based on device characteristics previously stored in the database for a first subset of the second set of circuit elements and determining device characteristics for a second subset of the second set of circuit elements using one of an aging simulation or a stress simulation; and a circuit generation system, coupled to the at least one processor, the circuit generation system configured to form a circuit on a substrate, wherein the circuit includes at least one of the first set of circuit elements or the second set of circuit elements.

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