公开(公告)号：US20170133321A9

公开(公告)日：2017-05-11

申请号：US13859797

申请日：2013-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yeh YU ,  Yuan-Te HOU ,  Chung-Min FU ,  Wen-Hao CHEN ,  Wan-Yu LO

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

公开(公告)号：US20150121329A1

公开(公告)日：2015-04-30

申请号：US14068064

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Min FU ,  Yung-Fong LU ,  Chung-Hsing WANG

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout.

Abstract translation: 一种方法包括提供包括表示电路元件的多个单元的半导体器件的第一布局，以及在处理器中提供包括多个单元的单元库。 电路元件包括多个鳍式场效应晶体管（Fin-FET）。 单元库中的多个单元格中的每个单元都显示有指示相应的翅片高度的分别不同的标记。 该方法还包括通过在第一布局中的相应位置放置或替换来自单元库的至少一个单元来产生要制造的半导体器件的第二布局。 来自电池库的至少一个电池包括在第二布局中具有与相邻Fin-FET不同的散热片高度的Fin-FET。

公开(公告)号：US20140264924A1

公开(公告)日：2014-09-18

申请号：US13859797

申请日：2013-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yeh YU ,  Yuan-Te HOU ,  Chung-Min FU ,  Wen-Hao CHEN ,  Wan-Yu LO

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

Abstract translation: 集成电路结构包括用于集成电路的多个电源或接地导轨，在平面上垂直分离的多个电源或接地导轨，多个电源轨之间或多个接地导轨之间或多个接地导轨之间的多个功能单元，或两者之间 以及在垂直分离的电源轨或接地轨之间的跨接连接，多个功能单元之间的垂直对齐的间隙内的跨接连接。 在集成电路中减轻IR滴落和电迁移影响的方法包括在集成电路布局的平面的不同的垂直级上形成多个电源轨或接地轨，每个电源轨或接地轨与跳线连接 至少两个电源轨或两个接地轨，所述跨接线连接在所述集成电路的单元之间的垂直对齐的间隙内。

公开(公告)号：US20140101626A1

公开(公告)日：2014-04-10

申请号：US14101448

申请日：2013-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yeh YU ,  Chung-Min FU ,  Ping-Heng YEH

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5081

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.

Abstract translation: 计算机实现的方法包括访问存储在有形的，非暂时的机器可读介质中的3D-IC模型，在计算机处理器中处理该模型以产生包含在操作下的3D-IC的多个点处的温度的温度图 条件; 识别电迁移（EM）额定因子，以及从处理器计算和输出表示每个点处的温度依赖EM电流约束的数据。

公开(公告)号：US20140223391A1

公开(公告)日：2014-08-07

申请号：US14251696

申请日：2014-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Min FU ,  Yung-Fong LU ,  Wen-Ju YANG ,  Chin-Chang HSU

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70

Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Abstract translation: 装置包括用于存储具有至少一个模板的模板库的机器可读存储介质。 该模板将包括通过多图案化IC的单层而形成的至少一个图案的第一布局图示。 该图案具有使用多个分别不同的光掩模形成的多个部分。 第一布局表示包括识别每个部分将要位于哪个光掩模上的数据。 电子设计自动化（EDA）工具包括被配置为接收电路的至少一部分的硬件描述语言表示并且生成具有多个多边形的电路的一部分的第二布局表示的处理器。 EDA工具具有匹配模块，其识别并输出多个部分中的一个或多个部分是否匹配多个多边形的子集的指示。

公开(公告)号：US20140059504A1

公开(公告)日：2014-02-27

申请号：US14068006

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huang-Yu CHEN ,  Yuan-Te HOU ,  Chung-Min FU ,  Chung-Hsing WANG ,  Wen-Hao CHEN ,  Yi-Kan CHENG

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract translation: 接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案 被包括在第二个光掩模中。 所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。 除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。 生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。 输出表示剩余的第一图案和替换图案的数据。