公开(公告)号：US07860152B2

公开(公告)日：2010-12-28

申请号：US12638468

申请日：2009-12-15

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

摘要翻译： 无线通信系统。 该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。 多个帧中的每一个包括主同步码（PCS）和辅同步码（SSC）。 编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。 编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。 第二序列从多个序列中选择。 多个序列中的每一个相对于多个序列中的所有其他序列是正交的。 第三序列包括来自第一序列的比特的子集。

公开(公告)号：US06366574B1

公开(公告)日：2002-04-02

申请号：US09086689

申请日：1998-05-28

申请人： Eric Baissus ,  Srinath Hosur ,  Anand G. Dabak

发明人： Eric Baissus ,  Srinath Hosur ,  Anand G. Dabak

IPC分类号： H04J306

CPC分类号： H04L7/10 ,  H04L7/0334 ,  H04L7/041 ,  H04L7/046

摘要： Device for recovering synchronization on a signal transmitted to a mobile-telephone receiver, including phase-estimator means (47, 49) for the absolute value (ABS) and the sign (SIGN) of the transmitted signal, estimation processor (64) for processing the output signals of the estimators (47, 49), a sequencer (67), one input of which is connected to the output of the processor (64) and one output of which applies a mode signal to the processor, another output of the sequencer (67) being connected via a sampling-time generator (68) to the sampling-time control inputs of the estimators (47, 49).

摘要翻译： 用于恢复发送到移动电话接收机的信号的同步的装置，包括用于绝对值（ABS）的相位估计装置（47,49）和发送信号的符号（SIGN），用于处理的估计处理器 估计器（47,49）的输出信号，定序器（67），其一个输入端连接到处理器（64）的输出，其一个输出端向处理器施加模式信号，另一个输出端 定序器（67）经由采样时间发生器（68）连接到估计器（47,49）的采样时间控制输入端。

公开(公告)号：US06345069B1

公开(公告)日：2002-02-05

申请号：US09217759

申请日：1998-12-21

申请人： Anand G. Dabak ,  Srinath Hosur ,  Sundararajan Sriram

发明人： Anand G. Dabak ,  Srinath Hosur ,  Sundararajan Sriram

IPC分类号： A61F206

CPC分类号： H04B1/70757 ,  H04B1/70735 ,  H04B1/7093 ,  H04B2201/70707

摘要： A circuit for detecting a signal is designed with a first serial circuit coupled to receive an input signal in response to a clock signal. The first serial circuit (121) has N taps (142-146) arranged to produce a respective plurality of first tap signals from the input signal (111). A first logic circuit (130, 132, 134, 148) is coupled to receive the plurality of first tap signals and one of N predetermined signals and the complement of N predetermined signals. The first logic circuit produces a first output signal (150) in response to the clock signal, the plurality of first tap signals and the one of N predetermined signals and the complement of N predetermined signals. A second serial circuit coupled to receive the first output signal. The second serial circuit has M taps (150, 172-184) arranged to produce a respective plurality of second tap signals from the first output signal, wherein a ratio of N/M is no greater than four. A second logic circuit (186) is coupled to receive one of a true and a complement of each of the plurality of second tap signals. The second logic circuit produces a second output signal (188) in response to the one of a true and a complement of each of the plurality of second tap signals.

摘要翻译： 用于检测信号的电路被设计成具有耦合以响应于时钟信号接收输入信号的第一串行电路。 第一串行电路（121）具有N个抽头（142-146），用于从输入信号（111）产生相应的多个第一抽头信号。 第一逻辑电路（130,132,134,148）被耦合以接收多个第一抽头信号以及N个预定信号中的一个以及N个预定信号的互补。 第一逻辑电路响应于时钟信号，多个第一抽头信号和N个预定信号中的一个以及N个预定信号的互补产生第一输出信号（150）。 耦合以接收第一输出信号的第二串行电路。 所述第二串行电路具有配置成从所述第一输出信号产生相应的多个第二抽头信号的M个抽头（150,172-184），其中N / M的比率不大于4。 第二逻辑电路（186）被耦合以接收多个第二抽头信号中的每一个的真实和补码中的一个。 所述第二逻辑电路响应于所述多个第二抽头信号中的每一个的真和互补中的一个产生第二输出信号（188）。

公开(公告)号：US08917756B2

公开(公告)日：2014-12-23

申请号：US13403223

申请日：2012-02-23

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713 ,  H04B1/7083 ,  H04B1/7073 ,  H04J13/00 ,  H04J13/12

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

公开(公告)号：US20120147877A1

公开(公告)日：2012-06-14

申请号：US13403201

申请日：2012-02-23

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04W56/00 ,  H04B7/216

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

公开(公告)号：US20110064071A1

公开(公告)日：2011-03-17

申请号：US12949413

申请日：2010-11-18

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04J3/06

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

摘要翻译： 无线通信系统。 该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。 多个帧中的每一个包括主同步码（PCS）和辅同步码（SSC）。 编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。 编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。 第二序列从多个序列中选择。 多个序列中的每一个相对于多个序列中的所有其他序列是正交的。 第三序列包括来自第一序列的比特的子集。

公开(公告)号：US20100091821A1

公开(公告)日：2010-04-15

申请号：US12638468

申请日：2009-12-15

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/707

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

摘要翻译： 无线通信系统。 该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。 多个帧中的每一个包括主同步码（PCS）和辅同步码（SSC）。 编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。 编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。 第二序列从多个序列中选择。 多个序列中的每一个相对于多个序列中的所有其他序列是正交的。 第三序列包括来自第一序列的比特的子集。

公开(公告)号：US07693227B2

公开(公告)日：2010-04-06

申请号：US11389354

申请日：2006-03-23

申请人： Badri N. Varadarajan ,  Anand G. Dabak ,  Charles Sestok ,  Srinath Hosur

发明人： Badri N. Varadarajan ,  Anand G. Dabak ,  Charles Sestok ,  Srinath Hosur

IPC分类号： H04L27/28

CPC分类号： H04L25/0216 ,  H04L27/2662 ,  H04L2025/03414

摘要： A method of estimating a channel length (304) in a wireless receiver is disclosed. The receiver receives a signal (122) from a remote transmitter. The receiver selects a plurality (K) of different candidate channel lengths and determines a respective criterion value (402) of the signal for each of the plurality of different candidate channel lengths. The receiver selects a channel length (410) from the plurality of different candidate channel lengths in response to the respective criterion value (404).

摘要翻译： 公开了一种在无线接收机中估计信道长度（304）的方法。 接收机从远程发射机接收信号（122）。 接收机选择不同候选信道长度的多个（K），并且为多个不同候选信道长度中的每一个确定信号的相应标准值（402）。 接收机响应于各自的标准值（404）从多个不同的候选信道长度中选择信道长度（410）。

公开(公告)号：US07656934B2

公开(公告)日：2010-02-02

申请号：US11438149

申请日：2006-05-22

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

公开(公告)号：US07302018B2

公开(公告)日：2007-11-27

申请号：US10447978

申请日：2003-05-29

申请人： Eko N. Onggosanusi ,  Srinath Hosur ,  Anand G. Dabak

发明人： Eko N. Onggosanusi ,  Srinath Hosur ,  Anand G. Dabak

IPC分类号： H04L27/06

CPC分类号： H04B1/71055 ,  H04B1/71072 ,  H04L25/03171

摘要： Iterative detection for a MIMO (multiple-input, multiple-output) wireless communications system uses multiple stages for interference cancellation refinements. Detection is determined by maximizing signal to noise plus interference ratios. Equalization matrix updating uses a matrix-inversion-free recursion. For P transmitter antennas and Q receiver antennas, the soft symbol vector estimates are z=Fr−Gshard with F a P×Q IMMSE detector, r the received Q vector, and G a P×P interference canceller with shard hard decisions of prior symbols and iterations.

摘要翻译： MIMO（多输入多输出）无线通信系统的迭代检测使用多个阶段进行干扰消除改进。 通过最大化信噪比加干扰比来确定检测。 均衡矩阵更新使用矩阵无倒数递归。 对于P发射机天线和Q接收机天线，软符号矢量估计是具有F a PxQ IMMSE检测器的z = Fr-Gs ，接收到的Q矢量，以及具有s个发射机天线的G a PxP干扰消除器， SUP> hard 硬判决先前的符号和迭代。