公开(公告)号：US07103085B1

公开(公告)日：2006-09-05

申请号：US09595561

申请日：2000-06-16

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/38

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

摘要翻译： 无线通信系统。 该系统包括发射机电路（BST1），发射机电路包括用于传输多个帧（FR）的编码器电路（50）。 多个帧中的每一个包括主同步码（PCS）和辅同步码（SSC）。 编码器电路包括用于响应于第一序列（32）提供主同步码的电路（50 1）。 编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（50）。 第二序列从多个序列中选择。 多个序列中的每一个相对于多个序列中的所有其他序列是正交的。 第三序列包括来自第一序列的比特的子集。

公开(公告)号：US08923362B2

公开(公告)日：2014-12-30

申请号：US13403201

申请日：2012-02-23

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713 ,  H04B1/7083 ,  H04B1/7073 ,  H04J13/00 ,  H04J13/12

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

公开(公告)号：US08681834B2

公开(公告)日：2014-03-25

申请号：US13403236

申请日：2012-02-23

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

摘要翻译： 无线通信系统。 该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。 多个帧中的每一个包括主同步码（PCS）和第二同步码（SSC）。 编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。 编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。 第二序列从多个序列中选择。 多个序列中的每一个相对于所有其他序列是正交的。 第三个序列是来自第一个序列的比特的子集。

公开(公告)号：US08144747B2

公开(公告)日：2012-03-27

申请号：US12949413

申请日：2010-11-18

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

摘要翻译： 无线通信系统。 该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。 多个帧中的每一个包括主同步码（PCS）和辅同步码（SSC）。 编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。 编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。 第二序列从多个序列中选择。 多个序列中的每一个相对于多个序列中的所有其他序列是正交的。 第三序列包括来自第一序列的比特的子集。

公开(公告)号：US06996162B1

公开(公告)日：2006-02-07

申请号：US09679487

申请日：2000-10-04

申请人： Srinath Hosur ,  Sundararajan Sriram ,  Anand G. Dabak ,  Alan Gatherer

发明人： Srinath Hosur ,  Sundararajan Sriram ,  Anand G. Dabak ,  Alan Gatherer

IPC分类号： H04B1/69 ,  H04L7/00

CPC分类号： H04B1/7077 ,  H04B1/70755 ,  H04B1/7083

摘要： A method (70) of operating a wireless receiver (UST). The method receives a wireless communicated signal, wherein the signal comprises a first synchronization channel component. The method also correlates a synchronization channel value (PSC) to the signal to produce a plurality of correlation samples in response to a correlation between the synchronization channel value and the signal. Further, the method compares (72) the plurality of correlation samples to a threshold (τ) and stores as a first set of correlation samples selected ones of the plurality of correlation samples that exceed the threshold and are within a first time sample period, wherein each of the correlation samples in the first set has a corresponding sample time relative to the first time sample period. Finally, the method combines (74) a second set of correlation samples with the first set of correlation samples.

摘要翻译： 一种操作无线接收机（UST）的方法（70）。 该方法接收无线通信信号，其中信号包括第一同步信道分量。 该方法还将同步信道值（PSC）与信号相关联，以响应于同步信道值和信号之间的相关性而产生多个相关样本。 此外，该方法将（72）多个相关采样与阈值（τ）进行比较，并且存储作为超过阈值并且在第一时间采样周期内的多个相关样本中选择的一个相关样本的第一组相关样本，其中 第一组中的每个相关样本具有相对于第一时间采样周期的相应采样时间。 最后，该方法将第二组相关样本与第一组相关样本组合（74）。

公开(公告)号：US06834046B1

公开(公告)日：2004-12-21

申请号：US09679657

申请日：2000-10-04

申请人： Srinath Hosur ,  Sundararajan Sriram ,  Timothy M. Schmidl ,  Anand G. Dabak

发明人： Srinath Hosur ,  Sundararajan Sriram ,  Timothy M. Schmidl ,  Anand G. Dabak

IPC分类号： H04B7216

CPC分类号： H04B1/7083

摘要： A method (70) of operating a wireless receiver (UST). The method receives a wireless communicated signal, wherein the signal comprises asymmetrically spaced synchronization channel components. The method also defines (72) a set of signals from the communicated signal, wherein the set spans a number of equal duration time slots and comprises at least a first synchronization channel component and a second synchronization channel component. The method also forms (76) a first signal combination by combining a first portion of the set of signals with a second portion of the set of signals, and it forms (78) a second signal combination by combining a third portion of the set of signals with a fourth portion of the set of signals. Finally, the method detects (80, 82, 84) a location of the first synchronization channel component and a location of the second synchronization channel component in response to at least one of the first and second signal combinations.

摘要翻译： 一种操作无线接收机（UST）的方法（70）。 该方法接收无线通信信号，其中该信号包括不对称间隔的同步信道分量。 该方法还定义（72）来自所传送的信号的一组信号，其中该组跨越多个相等的持续时间时隙，并且包括至少第一同步信道分量和第二同步信道分量。 该方法还通过将该组信号的第一部分与该组信号的第二部分组合来形成（76）第一信号组合，并且它通过组合第二信号组合的第三部分来形成（78）第二信号组合 信号与该组信号的第四部分。 最后，响应于第一和第二信号组合中的至少一个，该方法检测（80,82,84）第一同步信道分量的位置和第二同步信道分量的位置。

公开(公告)号：US20120147730A1

公开(公告)日：2012-06-14

申请号：US13403236

申请日：2012-02-23

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04J11/00

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

公开(公告)号：US07860152B2

公开(公告)日：2010-12-28

申请号：US12638468

申请日：2009-12-15

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

摘要翻译： 无线通信系统。 该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。 多个帧中的每一个包括主同步码（PCS）和辅同步码（SSC）。 编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。 编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。 第二序列从多个序列中选择。 多个序列中的每一个相对于多个序列中的所有其他序列是正交的。 第三序列包括来自第一序列的比特的子集。

公开(公告)号：US06345069B1

公开(公告)日：2002-02-05

申请号：US09217759

申请日：1998-12-21

申请人： Anand G. Dabak ,  Srinath Hosur ,  Sundararajan Sriram

发明人： Anand G. Dabak ,  Srinath Hosur ,  Sundararajan Sriram

IPC分类号： A61F206

CPC分类号： H04B1/70757 ,  H04B1/70735 ,  H04B1/7093 ,  H04B2201/70707

摘要： A circuit for detecting a signal is designed with a first serial circuit coupled to receive an input signal in response to a clock signal. The first serial circuit (121) has N taps (142-146) arranged to produce a respective plurality of first tap signals from the input signal (111). A first logic circuit (130, 132, 134, 148) is coupled to receive the plurality of first tap signals and one of N predetermined signals and the complement of N predetermined signals. The first logic circuit produces a first output signal (150) in response to the clock signal, the plurality of first tap signals and the one of N predetermined signals and the complement of N predetermined signals. A second serial circuit coupled to receive the first output signal. The second serial circuit has M taps (150, 172-184) arranged to produce a respective plurality of second tap signals from the first output signal, wherein a ratio of N/M is no greater than four. A second logic circuit (186) is coupled to receive one of a true and a complement of each of the plurality of second tap signals. The second logic circuit produces a second output signal (188) in response to the one of a true and a complement of each of the plurality of second tap signals.

摘要翻译： 用于检测信号的电路被设计成具有耦合以响应于时钟信号接收输入信号的第一串行电路。 第一串行电路（121）具有N个抽头（142-146），用于从输入信号（111）产生相应的多个第一抽头信号。 第一逻辑电路（130,132,134,148）被耦合以接收多个第一抽头信号以及N个预定信号中的一个以及N个预定信号的互补。 第一逻辑电路响应于时钟信号，多个第一抽头信号和N个预定信号中的一个以及N个预定信号的互补产生第一输出信号（150）。 耦合以接收第一输出信号的第二串行电路。 所述第二串行电路具有配置成从所述第一输出信号产生相应的多个第二抽头信号的M个抽头（150,172-184），其中N / M的比率不大于4。 第二逻辑电路（186）被耦合以接收多个第二抽头信号中的每一个的真实和补码中的一个。 所述第二逻辑电路响应于所述多个第二抽头信号中的每一个的真和互补中的一个产生第二输出信号（188）。

公开(公告)号：US08917756B2

公开(公告)日：2014-12-23

申请号：US13403223

申请日：2012-02-23

申请人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

发明人： Anand G. Dabak ,  Sundararajan Sriram ,  Srinath Hosur

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713 ,  H04B1/7083 ,  H04B1/7073 ,  H04J13/00 ,  H04J13/12

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04J13/00 ,  H04J13/12

摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.