公开(公告)号：US20080301599A1

公开(公告)日：2008-12-04

申请号：US11757335

申请日：2007-06-01

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： H01L21/823412 ,  G06F17/5036 ,  H01L21/823425 ,  H01L27/0207

摘要： An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.

摘要翻译： 用于估计集成电路布局中阈值电压的布局引起的变化的自动化方法。 该方法开始于在布局内选择扩散区域以进行分析的步骤。 然后，系统识别所选区域的Si / STI边缘以及通道区域及其相关的栅极/ Si边缘。 接下来，识别每个识别的通道区域中的阈值电压变化，这需要由于纵向方向的影响而计算阈值电压变化的进一步步骤; 计算由于横向影响引起的阈值电压变化; 并且将纵向和横向变化组合以提供整体变化。 最后，通过组合来自各个通道变化的变化来确定总体变化。

公开(公告)号：US20080296698A1

公开(公告)日：2008-12-04

申请号：US11757294

申请日：2007-06-01

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L29/78

CPC分类号： H01L21/823412 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/7833

摘要： A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout

摘要翻译： 一种用于平滑集成电路布局中阈值电压变化的方法。 该方法开始于识别与布局中的晶体管相关联的重组表面。 处理这种复合表面以影响与这些表面相邻的间隙原子的重组，从而最小化布局内的晶体管的阈值电压的变化

公开(公告)号：US08762924B2

公开(公告)日：2014-06-24

申请号：US12510188

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

摘要翻译： 粗略地描述了一种用于近似集成电路布局中的沟道区域中的应力诱导迁移率增强的方法，包括近似在通道中的多个采样点中的每一个处的应力，将每个采样点处的应力近似转换为 相应的移动性增强值，并在所有采样点平均移动性增强值。 该方法实现了集成电路应力分析，其考虑了由多个应力产生机制所产生的应力，具有沿通道长度以外的矢量分量的应力，以及由于在邻域中存在其它结构的应力贡献（包括缓解） 正在研究的频道区域，除了最接近的STI接口。 该方法还能够对大型布局区域甚至全芯片布局进行应力分析，而不会导致完整TCAD仿真的计算成本。

公开(公告)号：US08713510B2

公开(公告)日：2014-04-29

申请号：US12510185

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US08407634B1

公开(公告)日：2013-03-26

申请号：US11291294

申请日：2005-12-01

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F9/45

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US07691693B2

公开(公告)日：2010-04-06

申请号：US11757294

申请日：2007-06-01

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： H01L21/338

CPC分类号： H01L21/823412 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/7833

摘要： A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout.

摘要翻译： 一种用于平滑集成电路布局中阈值电压变化的方法。 该方法开始于识别与布局中的晶体管相关联的重组表面。 处理这种复合表面以影响与这些表面相邻的间隙原子的重组，从而最小化布局内晶体管的阈值电压的变化。

公开(公告)号：US20100023902A1

公开(公告)日：2010-01-28

申请号：US12510190

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US08881073B1

公开(公告)日：2014-11-04

申请号：US13850133

申请日：2013-03-25

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US08615728B2

公开(公告)日：2013-12-24

申请号：US12510190

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50 ,  G06F7/60 ,  G06F17/10 ,  G06F9/455 ,  G06F11/22 ,  G06G7/62

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US08413096B2

公开(公告)日：2013-04-02

申请号：US12510187

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.