公开(公告)号：US06429700B1

公开(公告)日：2002-08-06

申请号：US09836153

申请日：2001-04-17

申请人： Jungwook Yang

发明人： Jungwook Yang

IPC分类号： H03K300

CPC分类号： H03F3/45511 ,  H03F2203/45401 ,  H03F2203/45402 ,  H03F2203/45424 ,  H03F2203/45426 ,  H03F2203/45431 ,  H03F2203/45696 ,  H03F2203/45702

摘要： A driver circuit having a minimized and/or controllable output common mode voltage comprises a differential amplifier having, a passive element as a biasing source for establishing a bias current in the differential amplifier and a control amplifier operatively coupled to the differential amplifier in a feedback arrangement, the control amplifier generating a control signal. The differential amplifier is responsive to the control signal for providing a voltage at an output of the driver circuit that is substantially independent of an input signal presented to an input of the driver circuit. By eliminating the need for an active device (e.g., transistor) as a bias current source, the output common mode voltage of the driver circuit is minimized. A reference signal coupled to the control amplifier, in conjunction with the feedback arrangement, substantially fixes the output common mode voltage of the driver circuit to a predetermined value.

摘要翻译： 具有最小化和/或可控制的输出共模电压的驱动器电路包括差分放大器，其具有作为用于在差分放大器中建立偏置电流的偏置源的无源元件和在反馈布置中可操作地耦合到差分放大器的控制放大器 ，所述控制放大器产生控制信号。 差分放大器响应于控制信号，以在驱动器电路的输出处提供基本上与呈现给驱动器电路的输入的输入信号无关的电压。 通过消除对作为偏置电流源的有源器件（例如，晶体管）的需要，驱动器电路的输出共模电压最小化。 耦合到控制放大器的参考信号结合反馈装置基本上将驱动器电路的输出共模电压固定为预定值。

公开(公告)号：US06388602B1

公开(公告)日：2002-05-14

申请号：US09643956

申请日：2000-08-23

申请人： Jungwook Yang

发明人： Jungwook Yang

IPC分类号： H03M136

CPC分类号： H03M1/0687 ,  H03M1/0809 ,  H03M1/36 ,  H03M7/165

摘要： An encoding circuit for use with a comparator, includes a plurality of logic elements for receiving an input from a comparator, and a Gray code encoder for receiving an output from the plurality of logic elements. Both first and second type comparator errors (e.g., meta-stability errors and bubble-errors) are substantially eliminated simultaneously by the logic elements.

摘要翻译： 一种与比较器一起使用的编码电路，包括用于从比较器接收输入的多个逻辑元件和用于接收来自多个逻辑元件的输出的格雷码编码器。 逻辑元件同时实质上消除了第一和第二类型比较器错误（例如元稳定性误差和气泡误差）。

公开(公告)号：US6111430A

公开(公告)日：2000-08-29

申请号：US104602

申请日：1998-06-24

申请人： Daniel M. Kuchta ,  Jungwook Yang

发明人： Daniel M. Kuchta ,  Jungwook Yang

IPC分类号： H03K19/0185 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/20

CPC分类号： H03K19/018535

摘要： A circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises a depletion mode MESFET device, coupled between at least one CMOS device and at least one other MESFET device, the depletion mode MESFET device limiting a current through a gate-source junction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of the at least one other MESFET device. Another circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises: a source follower MESFET device coupled to an output terminal of at least one CMOS device; a first depletion mode MESFET device, coupled to the source follower MESFET device, the first depletion mode MESFET device limiting a current through a gate-source juction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of at least one other MESFET device; and a second depletion mode MESFET device, coupled to the first depletion mode MESFET device, for providing a discharge path; wherein an input terminal of the at least one other MESFET device is coupled between the first and second depletion mode MESFET devices.

摘要翻译： 用于与具有与其相关联的输入电平范围的MESFET逻辑器件具有与其相关联的具有输出电平范围的CMOS逻辑器件的电路包括耗尽型MESFET器件，耦合在至少一个CMOS器件与至少一个其它MESFET器件 耗尽型MESFET器件限制通过栅极 - 源极结的电流，使得至少一个CMOS器件的输出电平范围被改变为与至少一个其它MESFET器件的输入电平范围兼容。 用于与具有与其相关联的输入电平范围的具有MESFET逻辑器件的具有与其相关联的输出电平范围的CMOS逻辑器件的接口的另一电路包括：耦合到至少一个CMOS器件的输出端的源极跟随器MESFET器件; 耦合到源极跟随器MESFET器件的第一耗尽型MESFET器件，第一耗尽型MESFET器件限制通过栅极源极漏极的电流，使得至少一个CMOS器件的输出电平范围被改变为与 至少一个其它MESFET器件的输入电平范围; 以及耦合到所述第一耗尽型MESFET器件的用于提供放电路径的第二耗尽型MESFET器件; 其中所述至少一个其它MESFET器件的输入端耦合在所述第一和第二耗尽型MESFET器件之间。