公开(公告)号：US09214948B2

公开(公告)日：2015-12-15

申请号：US14255912

申请日：2014-04-17

Applicant: Cirrus Logic, Inc.

Inventor： Ku He ,  Xin Zhao ,  Xiaofan Fei

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/36

CPC classification number: H03M1/002 ,  H03M1/0809 ,  H03M1/181 ,  H03M1/36

Abstract: A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on.

Abstract translation: 用于模数转换器（ADC）的比较器跟踪方案可以通过随时间变化多个比较器供电以将模拟输入信号转换为数字输出信号来实现动态窗口尺寸。 比较器跟踪方案可以例如在耦合到ADC中的多个比较器的控制器中实现。 例如，控制器可以确定ADC的窗口大小并确定ADC的窗口位置。 然后，控制器可以在以窗口位置为中心并且具有窗口大小的宽度的窗口内激活ADC的比较器。 控制器可以通过分析滤波器的输出来确定窗口大小。 当滤波器输出指示快速变化的模拟输入信号时，控制器可以动态增加ADC的窗口大小，这可能会增加多个比较器上电。

公开(公告)号：US08810442B1

公开(公告)日：2014-08-19

申请号：US13766948

申请日：2013-02-14

Applicant: PMC-Sierra US, Inc.

Inventor： Anthony Eugene Zortea

IPC: H03M1/08

CPC classification number: H03M1/06 ,  H03M1/0809 ,  H03M1/361

Abstract: A method of background calibration of aperture center errors in a data communication system is provided. In an implementation, in response to detection of a low sampler output (“0”) in between two high sampler outputs (“1”), the method includes: calculating a signal derivative of an ADC output signal at the time of the detected low output; and adjusting timing at a selected sampler based on the calculated signal derivative. In an example implementation, the method includes watching for bubbles in the thermometer code output, and estimating the first derivative of the signal at the time of the bubble, then estimating the sign of the errors. In an example implementation, the errors are used in a control loop to reduce the aperture center error.

Abstract translation: 提供了一种数据通信系统中孔径中心误差的背景校准方法。 在一个实现中，响应于检测两个高采样器输出（“1”）之间的低采样器输出（“0”），该方法包括：在检测到的低电平时计算ADC输出信号的信号导数 输出; 以及基于所计算的信号导数来调整所选采样器的定时。 在示例实现中，该方法包括观察温度计代码输出中的气泡，以及估计气泡时的信号的一阶导数，然后估计误差的符号。 在一个示例实现中，错误用于控制环路以减小光圈中心误差。

公开(公告)号：US20110316629A1

公开(公告)日：2011-12-29

申请号：US12822811

申请日：2010-06-24

Applicant: Bo ZHANG

Inventor： Bo ZHANG

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45188 ,  H03F3/4521 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2203/45212 ,  H03F2203/45466 ,  H03F2203/45588 ,  H03F2203/45702 ,  H03M1/0809 ,  H03M1/365

Abstract: An offset cancellation circuit for canceling an offset voltage in an amplifier is provided herein. The offset cancellation circuit includes a current source configured to provide an offset current, a switching stage comprising first and second switches, and a cascode stage. The cascode stage comprises a first cascode device configured to receive the offset current from the first switch and inject the offset current into a first differential end of the amplifier, and a second cascode device configured to receive the offset current from the second switch and inject the offset current into a second differential end of the amplifier. Offset voltages are common to many differential circuits as a result of mismatch. The injection of current by the offset cancellation circuit can reduce or eliminate an offset voltage, while the cascode stage can prevent parasitic capacitance associated with the offset cancellation circuit from creating further mismatch.

Abstract translation: 本文提供了用于消除放大器中的偏移电压的偏移消除电路。 偏移消除电路包括被配置为提供偏移电流的电流源，包括第一和第二开关的开关级和共源共栅级。 共源共栅级包括第一共源共栅器件，其被配置为从第一开关接收偏移电流，并将偏移电流注入放大器的第一差分端，以及第二共源共栅器件，其被配置为从第二开关接收偏移电流， 将电流偏移到放大器的第二差分端。 由于失配，许多差分电路的偏移电压是常见的。 通过偏移消除电路注入电流可以减少或消除偏移电压，而共源共栅级可以防止与偏移消除电路相关联的寄生电容产生进一步的失配。

公开(公告)号：US07893855B2

公开(公告)日：2011-02-22

申请号：US12485924

申请日：2009-06-17

Applicant: Sheng-Jui Huang

Inventor： Sheng-Jui Huang

IPC: H03M3/00

CPC classification number: H03F3/45475 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/4565 ,  H03F3/45932 ,  H03F2200/408 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45514 ,  H03F2203/45562 ,  H03F2203/45594 ,  H03F2203/45644 ,  H03H11/1252 ,  H03H11/1291 ,  H03M1/0663 ,  H03M1/0809 ,  H03M1/206 ,  H03M1/361 ,  H03M1/806 ,  H03M3/424 ,  H03M3/448 ,  H03M3/464

Abstract: An exemplary continuous-time delta-sigma analog-to-digital converter includes a loop filter, a quantizer, a dynamic element matching circuit, a latch, and a digital-to-analog converter (DAC). The loop filter contains a plurality of integrators coupled in series, including a first integrator and a second integrator; a first positive feedback resistive element, placed in a first positive feedback path between a first output node of the second integrator and a first input node of the first integrator; and a first negative feedback resistive element, placed in a first negative feedback path between a second output node of the second integrator and a second input node of the first integrator. The quantizer is implemented using a domino quantizer. The DAC contains a plurality of DAC units each having a capacitive device, a resistive device, and a switch device coupled between the capacitive device and the resistive device.

Abstract translation: 示例性连续时间Δ-Σ模数转换器包括环路滤波器，量化器，动态元件匹配电路，锁存器和数模转换器（DAC）。 环路滤波器包括串联耦合的多个积分器，包括第一积分器和第二积分器; 第一正反馈电阻元件，放置在第二积分器的第一输出节点与第一积分器的第一输入节点之间的第一正反馈路径中; 以及第一负反馈电阻元件，放置在第二积分器的第二输出节点与第一积分器的第二输入节点之间的第一负反馈路径中。 量化器使用多米诺量化器实现。 DAC包含多个DAC单元，每个DAC单元均具有电容性器件，电阻器件和耦合在电容器件和电阻器件之间的开关器件。

公开(公告)号：US20080186214A1

公开(公告)日：2008-08-07

申请号：US11755011

申请日：2007-05-30

Applicant: Seetharaman Janakiraman

Inventor： Seetharaman Janakiraman

IPC: H03M1/14

CPC classification number: H03M1/0809 ,  H03M1/38

Abstract: Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored in a storage element. An error signal is then generated, with the error signal representing a deviation of an expected digital code for the strength of a sample of an analog input from a value that would be generated without correction. The error signal is then added to the stored sample. In an embodiment implemented in the context of a SAR ADC, a digital value representing an integral non-linearity error is generated based on a partial digital code (result of a partial conversion of the sample) and an error coefficient. The digital value is converted to analog form by an auxiliary DAC, and added to the stored input sample.

Abstract translation: 导致产生的数字代码偏离预期值的模数转换器中的错误被更正。 模拟信号的样本被存储在存储元件中。 然后产生误差信号，其中误差信号表示模拟输入的样本的强度的预期数字代码与将被产生而不进行校正的值的偏差。 然后将误差信号添加到存储的样品。 在SAR ADC的上下文中实现的实施例中，基于部分数字码（样本的部分转换的结果）和误差系数来生成表示积分非线性误差的数字值。 数字值由辅助DAC转换为模拟形式，并添加到存储的输入采样。

公开(公告)号：US20070285301A1

公开(公告)日：2007-12-13

申请号：US11889777

申请日：2007-08-16

Applicant: Hiroyuki Nakamoto ,  Kunihiko Gotoh

Inventor： Hiroyuki Nakamoto ,  Kunihiko Gotoh

IPC: H03M1/36

CPC classification number: H03M1/0809 ,  H03M1/165 ,  H03M1/361 ,  H03M7/165

Abstract: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.

公开(公告)号：US06603415B1

公开(公告)日：2003-08-05

申请号：US09919411

申请日：2001-07-30

Applicant: Shyam S Somayajula

Inventor： Shyam S Somayajula

IPC: H03M106

CPC classification number: H03M1/0809 ,  H03M1/068 ,  H03M1/0863 ,  H03M1/1023 ,  H03M1/1215 ,  H03M1/462

Abstract: Metastable compensation circuitry 700 for detecting and compensating for metastable states of a regenerative latch 209 in a charge redistribution analog to digital converter 201. First and second latches 701a,b each having a selected threshold voltage for monitor corresponding first and second outputs of regenerative latch 209. Detection logic 202a,b 703 detects a selected output state of the first and second latches corresponding to a metastable state of regenerative latch 209. Suppression logic 703 generates an output of a selected logic level in response to the detection of a metastable state by detection logic 702/703.

Abstract translation: 用于检测和补偿电荷再分配模数转换器201中的再生锁存器209的亚稳态的可逆稳定补偿电路700.每个具有选择的阈值电压的第一和第二锁存器701a，b，用于监视对应的再生锁存器209的第一和第二输出 检测逻辑202a，b703检测对应于再生锁存器209的亚稳状态的第一和第二锁存器的选择的输出状态。抑制逻辑电路703响应于通过检测的亚稳态的检测而产生所选逻辑电平的输出 逻辑702/703。

公开(公告)号：US20020044077A1

公开(公告)日：2002-04-18

申请号：US09906816

申请日：2001-07-18

Applicant: Fujitsu Limited

Inventor： Sanroku Tsukamoto

IPC: H03M007/04

CPC classification number: H03M1/0687 ,  H03M1/0809 ,  H03M1/1095 ,  H03M1/365 ,  H03M13/47

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

Abstract translation: 高速A / D转换器包括用于将温度计代码转换为灰度代码的一系列编码器部分和用于检测灰度代码中的错误信号的误差信号产生部分，并产生指示这种混淆误差的误差信号。 误差校正部分根据误差信号校正灰度代码中的错误。 然后将经校正的灰度码转换为具有灰度码的二进制码到二进制码转换器。 当将高速A / D转换器并入半导体器件中时，可以使用具有相对于输入模拟信号连续变化的相位的采样时钟来测试A / D转换器，以对模拟信号进行采样，然后评估 相应产生的数字信号。

公开(公告)号：US06331828B1

公开(公告)日：2001-12-18

申请号：US09377314

申请日：1999-08-19

Applicant: Hiroyuki Kawasaki

Inventor： Hiroyuki Kawasaki

IPC: H03M702

CPC classification number: H03M1/0687 ,  H03M1/0809 ,  H03M1/365 ,  H03M1/46

Abstract: Between digital data signals, which are expressed using a notation system of three digit symmetric binary numbers (named “HEN2”), and analog signals, at least one way, mutual, or other conversions are made. Three digit symmetric binary numbers (HEN2), are a combination of signals in which at least one of two adjacent digits, at any digit position of one or more digits of 2-based three digit redundant binary numbers with one signal of three digits {n, o, p} expressing a value {−1, 0, 1} as a one-digit signal, is a signal “o” expressing zero. Thus three digits {−1, 0, 1} are used instead of the two digit {0, 1} binary system used in conventional A/D or D/A converters.

Abstract translation: 在使用三位数对称二进制数（“HEN2”）的符号系统表示的数字数据信号和模拟信号之间，进行至少一种方式，相互或其他转换。 三位数对称二进制数（HEN2）是这样的信号的组合，其中在两个三位数冗余二进制数的一个或多个位的任意数字位置处的两个相邻数字中的至少一个具有三位数{n ，o，p}表示作为一位数字信号的值{-1,0,1}是表示零的信号“o”。 因此，使用三位数{-1,0,1}代替常规A / D或D / A转换器中使用的两位数{0,1}二进制系统。

公开(公告)号：US5463395A

公开(公告)日：1995-10-31

申请号：US127373

申请日：1993-09-28

Applicant: Yasunori Sawai

Inventor： Yasunori Sawai

IPC: H03M1/08 ,  H03M1/14 ,  H03M1/36 ,  H03M1/68

CPC classification number: H03M1/0809 ,  H03M1/144 ,  H03M1/685

Abstract: A semi-flash type analog/digital converter for eliminating errors in its output signals which are caused by noise. The analog/digital converter includes a D/A converter for outputting a plurality of analog signals which are produced based on a plurality of input signals. A plurality of comparators compare the voltage of an analog input signal, provided via a sample and hold circuit, with the analog signals output from the D/A converter. The output from the comparators are supplied to two latches, which further provide the outputs to a plurality of encoders. One of the encoders encodes the signals provided by one of the latches and outputs signals representative of high order bits of a digital signal. A second encoder, which encodes output signals provided by the other latch, is a correction encoder. The correction encoder corrects the signals provided by the latch if it determines that any of the signals are in error, and outputs signals representing the lower order bits of a digital output signal. The correction encoder includes either a priority control circuit or an adder circuit which performs the correction.

Abstract translation: 半闪式模拟/数字转换器，用于消除由噪声引起的输出信号错误。 模拟/数字转换器包括用于输出基于多个输入信号产生的多个模拟信号的D / A转换器。 多个比较器将通过采样和保持电路提供的模拟输入信号的电压与从D / A转换器输出的模拟信号进行比较。 比较器的输出被提供给两个锁存器，这两个锁存器进一步向多个编码器提供输出。 一个编码器对由锁存器之一提供的信号进行编码，并输出表示数字信号的高位的信号。 编码由另一个锁存器提供的输出信号的第二编码器是校正编码器。 校正编码器校正锁存器提供的信号，如果它确定任何一个信号是错误的，并且输出表示数字输出信号的低位的信号。 校正编码器包括执行校正的优先控制电路或加法器电路。