-
公开(公告)号：US12230210B2
公开(公告)日：2025-02-18
申请号：US18547182
申请日：2022-09-30
Inventor： Liu Wu , Can Yuan , Zhidong Yuan , Cheng Xu , Luke Ding , Yongqian Li , Xiuting Liu
IPC: G09G3/3233 , H10K59/131
Abstract: A display substrate, including: a plurality of partition control signal lines disposed on a base substrate; and a plurality of sub-pixels disposed on the base substrate, at least one of the sub-pixels includes a pixel circuit and a light emitting device. The pixel circuit includes a switch transistor, a first partition control transistor, a drive transistor and a first initialization transistor. The first partition control transistor is electrically connected to the switch transistor, the first initialization transistor, the drive transistor and at least one partition control signal line. The first partition control transistor is configured to: in response to a partition control signal on the partition control signal line, selectively transmit a received first initialization signal to a gate electrode of the drive transistor in an initialization phase, and selectively transmit a received data signal to the gate electrode of the drive transistor in a data writing phase.
-
公开(公告)号：US12223900B2
公开(公告)日：2025-02-11
申请号：US18272811
申请日：2022-07-29
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan , Liu Wu , Xiuting Liu , Luke Ding , Cheng Xu , Miao Liu , Xing Yao
IPC: G09G3/3233 , G11C19/28 , H10K59/131
Abstract: A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.
-
公开(公告)号：US20250040353A1
公开(公告)日：2025-01-30
申请号：US18696953
申请日：2023-07-05
Inventor： Wenbin JIA , Zhijie YE
IPC: H10K59/122 , H10K59/12
Abstract: A display panel, a manufacturing method, and a display device are provided. The display panel includes a substrate and a pixel definition layer. The pixel definition layer includes multiple first barrier walls extending along a first direction and arranged along a second direction and multiple second barrier walls extending along the second direction and arranged along the first direction. The first direction and the second direction intersect. The first barrier walls include two edge barrier walls at two edges along the second direction, multiple intermediate barrier walls between the two edge barrier walls, and two separation barrier walls between the two edge barrier walls and respectively on two sides of the intermediate barrier walls along the second direction. The heights of the second barrier walls, the edge barrier walls and the separation barrier walls each is greater than the height of the intermediate barrier wall.
-
公开(公告)号：US12211448B2
公开(公告)日：2025-01-28
申请号：US17779164
申请日：2021-03-29
Inventor： Zhidong Yuan , Pan Xu , Yongqian Li , Can Yuan , Zhongyuan Wu
IPC: G11C19/00 , G09G3/32 , G09G3/3266 , G11C19/28
Abstract: A display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a plurality of stages of shift registers including at least one first shift register and at least one second shift register, and a plurality of clock signal lines including at least one first sub-clock signal line and at least one second sub-clock signal line. Each shift register includes a first sub-circuit and a second sub-circuit. A first sub-clock signal line in the at least one first sub-clock signal line is electrically connected to a first sub-circuit in a first shift register in the at least one first shift register. A second sub-clock signal line in the at least one second sub-clock signal line is electrically connected to one sub-circuit of a first sub-circuit and a second sub-circuit in a second shift register in the at least one second shift register.
-
425.发明授权公开(公告)号：US12211426B2
公开(公告)日：2025-01-28
申请号：US17922502
申请日：2021-09-08
Inventor： Huihui Li , Wenchao Bao , Song Meng , Jingbo Xu
IPC: G09G3/32
Abstract: An image dis play method applied to a display apparatus includes: establishing a correspondence table between a threshold voltage of a sub-pixel and a compensation voltage, the correspondence table including at least one adjustment interval, an adjustment interval including a first and second threshold voltage endpoint values, the first threshold voltage endpoint value being less than the second threshold voltage endpoint value; acquiring a threshold voltage of each sub-pixel; determining an adjustment interval in which the acquired threshold voltage is located according to the corresponding table; acquiring a compensation voltage corresponding to the acquired threshold voltage according to the correspondence table and the determined adjustment interval; and determining, in a case where the display apparatus is to display a black image, a data voltage required by each sub-pixel according to the acquired threshold voltage and the acquired compensation voltage.
-
Patent Agency Ranking
公开(公告)号：US20240397786A1
公开(公告)日：2024-11-28
申请号：US18269960
申请日：2021-12-27
Inventor： Liu WU , Yongqian LI , Can YUAN , Zhidong YUAN
IPC: H10K59/80 , H10K59/131 , H10K59/35
Abstract: Disclosed are a display substrate and a display apparatus, the display substrate includes a transparent region and a pixel region, the pixel region includes a plurality of light emitting devices, the plurality of light emitting devices include a first light emitting device, an orthographic projection of a first anode layer of the first light emitting device on a plane of the display substrate is partially overlapped with an orthographic projection of the transparent region on the plane of the display substrate, and an orthographic projection of a second anode layer of the first light emitting device on the plane of the display substrate is within a range of an orthographic projection of the pixel region on the plane of the display substrate.
-
427.发明授权公开(公告)号：US12156433B2
公开(公告)日：2024-11-26
申请号：US17289242
申请日：2020-08-20
Inventor： Wenbin Jia
IPC: H10K71/13 , H10K59/122 , H10K71/00
Abstract: A display substrate and a manufacturing method thereof, a display device, and an inkjet printing method. The display substrate comprises a base substrate. A pixel definition layer is provided at the base substrate. The pixel definition layer is provided with a pixel area for accommodating print drops. A stepped hole having a step shape is formed in the pixel area. The stepped hole comprises at least two steps. A barrier wall is provided inside the stepped hole to separate the adjacent steps.
-
428.发明申请公开(公告)号：US20240371454A1
公开(公告)日：2024-11-07
申请号：US18773836
申请日：2024-07-16
Inventor： Xuehuan FENG , Yongqian LI
IPC: G11C19/28
Abstract: A shift register includes a first scan unit including a first input circuit and a first output circuit, and a second scan unit including a second input circuit, a second output circuit, and a fourth transistor. The first input circuit is electrically connected to an input signal terminal and a first pull-up node. The first output circuit is electrically connected to the first pull-up node, a first clock signal terminal, a second clock signal terminal, a shift signal terminal, and a first scan signal terminal. The second input circuit is electrically connected to the input signal terminal and a second pull-up node. The second output circuit is electrically connected to the second pull-up node, a third clock signal terminal, and a second scan signal terminal. The fourth transistor is electrically connected to the second pull-up node, a sub-clock signal terminal, and a dummy shift signal terminal.
-
公开(公告)号：US20240365615A1
公开(公告)日：2024-10-31
申请号：US18765377
申请日：2024-07-08
Inventor： Luke DING , Yongqian LI
IPC: H10K59/131 , G09G3/3233 , H10K59/12 , H10K59/124
CPC classification number: H10K59/131 , G09G3/3233 , H10K59/1201 , H10K59/124 , G09G2300/0819 , G09G2300/0842 , G09G2310/08
Abstract: A display substrate and a preparation method therefor, and a display apparatus. The display substrate includes a base substrate, and a display area and a mounting area provided on the base substrate; the display area includes multiple second pixel circuits, the mounting area includes multiple first pixel circuits, and an area of an orthographic projection of a first pixel circuit on the base substrate is smaller than an area of an orthographic projection of a second pixel circuit on the base substrate.
-
公开(公告)号：US20240365595A1
公开(公告)日：2024-10-31
申请号：US18247230
申请日：2022-04-29
Inventor： Zhidong YUAN , Pan XU , Huifeng WANG , Can YUAN , Zhongyuan WU
IPC: H10K59/122 , H10K59/12 , H10K59/88
CPC classification number: H10K59/122 , H10K59/1201 , H10K59/88
Abstract: Embodiments of the present disclosure provide a display panel, a display device, and a method for preparing a display panel. The display panel has a display area and a peripheral area, the display panel including a pixel defining layer including a plurality of first pixel defining blocks in the display area parallelly arranged in a first direction, and adjacent first pixel defining blocks having different columns of pixel defining openings, and at least one second pixel defining block in the peripheral area as an extension of at least one first pixel defining block in a second direction to the peripheral area, each second pixel defining block including a plurality of columns of pixel defining openings, a column number which is greater than or equal to the difference in the column numbers of pixel defining openings of two adjacent first pixel defining blocks.
-
-
-
-
-
-
-
-
-
Search Results
511
records
(took 0.034 seconds)
