公开(公告)号：US12108039B2

公开(公告)日：2024-10-01

申请号：US18451694

申请日：2023-08-17

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186

CPC classification number: H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186

Abstract: An encoding method includes: changing values of luma pixels in a first block and a second block to filter a first boundary between the first block and the second block, using clipping such that change amounts of the respective values are within respective luma clip widths, the luma pixels in the first block and the second block being arranged along a first line across the first boundary; and changing values of chroma pixels in a third block and a fourth block to filter a second boundary between the third block and the fourth block, using clipping such that change amounts of the respective values are within respective chroma clip widths, the chroma pixels in the third block and the fourth block being arranged along a second line across the second boundary. The luma clip widths applied to the luma pixels are selected to be asymmetrical relative to the first boundary.

公开(公告)号：US12081749B2

公开(公告)日：2024-09-03

申请号：US18142166

申请日：2023-05-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Che-Wei Kuo ,  Kiyofumi Abe ,  Tadamasa Toma ,  Takahiro Nishi ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/51 ,  H04N19/80

CPC classification number: H04N19/117 ,  H04N19/176 ,  H04N19/51 ,  H04N19/80

Abstract: An encoder that encodes a current block to be encoded in an image is provided. The encoder includes: processor; and memory coupled to the processor, in which, in operation, the processor: generates a first prediction image based on a motion vector, the first prediction image being an image with full-pel precision; generates a second prediction image using an interpolation filter by interpolating a value at a fractional-pel position between full-pel positions included in the first prediction image; and encodes the current block based on the second prediction image, and in the using of the interpolation filter, the interpolation filter is switched between a first interpolation filter and a second interpolation filter differing in a total number of taps from the first interpolation filter.

公开(公告)号：US12052442B2

公开(公告)日：2024-07-30

申请号：US18133070

申请日：2023-04-11

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/70 ,  H04N19/169 ,  H04N19/423 ,  H04N19/46

CPC classification number: H04N19/70 ,  H04N19/188 ,  H04N19/423 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: writes, into a sequence parameter set which is header information of a sequence, video usability information syntax which is information for realizing an additional function in display of an image, and syntax different from the video usability information syntax. The syntax includes at least one parameter related to display timing of the image.

公开(公告)号：US12052436B2

公开(公告)日：2024-07-30

申请号：US18142173

申请日：2023-05-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Takashi Hashimoto

IPC: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in inter prediction processing: derives a first motion vector of a current block to be processed, using a motion vector of a previous block which has been previously processed; derives a second motion vector of the current block by performing motion estimation in the vicinity of the first motion vector; and generates a prediction image of the current block by performing motion compensation using the second motion vector.

公开(公告)号：US12028519B2

公开(公告)日：2024-07-02

申请号：US18071370

申请日：2022-11-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Che Wei Kuo ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/105 ,  H04N19/117 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186

CPC classification number: H04N19/117 ,  H04N19/105 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186 ,  H04N19/82

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. In the CCALF process, in response to a coordinate of the second reconstructed image sample being (x, y), coordinates of the first reconstructed image samples are (2x, 2y−1), (2x−1, 2y), (2x, 2y), (2x+1, 2y), (2x−1, 2y+1), (2x, 2y+1), (2x+1, 2y+1), and (2x, 2y+2).

公开(公告)号：US12028513B2

公开(公告)日：2024-07-02

申请号：US17463889

申请日：2021-09-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder includes: circuitry; and memory coupled to the circuitry, in which in operation, the circuitry: generates a prediction image of a current block to be processed, using a first motion vector; and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and in the updating of the HMVP table, the circuitry: determines whether a size of the current block is less than or equal to a threshold size; and skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size.

公开(公告)号：US12022072B2

公开(公告)日：2024-06-25

申请号：US17992833

申请日：2022-11-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hai Wei Sun ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Che-Wei Kuo ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/132 ,  H04N19/186 ,  H04N19/82

CPC classification number: H04N19/117 ,  H04N19/132 ,  H04N19/186 ,  H04N19/82

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component, generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component, and clips the second coefficient value. The circuitry generates a third coefficient value by adding the first coefficient value to the clipped second coefficient value, and clips the third coefficient value. The circuitry encodes a third reconstructed image sample of the chroma component using the clipped third coefficient value.

公开(公告)号：US12003759B2

公开(公告)日：2024-06-04

申请号：US18316944

申请日：2023-05-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/52 ,  H04N19/157 ,  H04N19/176 ,  H04N19/182 ,  H04N19/59

CPC classification number: H04N19/52 ,  H04N19/157 ,  H04N19/176 ,  H04N19/182 ,  H04N19/59

Abstract: An encoding method includes: determining a merge mode to be applied to a current block, the merge mode including a sub-block merge mode and a first merge mode, wherein in the merge mode, inter-prediction parameters are inferred from a neighboring block neighboring the current block, and wherein in the sub-block merge mode, the current block includes a plurality of sub-blocks, and inter-prediction parameters are provided for each of the plurality of sub-blocks; in response to the merge mode being determined to be the first merge mode, generating a prediction image for the current block by performing a bi-directional optical flow prediction process, wherein the bi-directional optical flow prediction process uses a spatial gradient for the current block; and in response to the merge mode being determined to be the sub-block merge mode, generating a prediction image for the current block by not performing the bi-directional optical flow prediction process.

公开(公告)号：US11962804B2

公开(公告)日：2024-04-16

申请号：US17373069

申请日：2021-07-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Han Boon Teo ,  Takahiro Nishi ,  Tadamasa Toma ,  Ru Ling Liao ,  Sughosh Pavan Shashidhar ,  Hai Wei Sun

IPC: H04N19/597 ,  G06T5/00 ,  H04N5/00 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46 ,  H04N19/85

CPC classification number: H04N19/597 ,  G06T5/006 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46 ,  H04N19/85

Abstract: An encoder capable of properly handling an image to be encoded or decoded includes processing circuitry and memory connected to the processing circuitry. Using the memory, the processing circuitry: obtains parameters including at least one of (i) one or more parameters related to a first process for correcting distortion in an image captured with a wide angle lens and (ii) one or more parameters related to a second process for stitching a plurality of images; generates an encoded image by encoding a current image to be processed that is based on the image or the plurality of images; and writes the parameters into a bitstream including the encoded image.

公开(公告)号：US11956466B2

公开(公告)日：2024-04-09

申请号：US18200782

申请日：2023-05-23

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N11/02 ,  H04N19/176 ,  H04N19/186 ,  H04N19/52

CPC classification number: H04N19/52 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: stores MV information and correction processing information into a FIFO buffer for an HMVP mode in association, the MV information being derived for a processed block and correction processing information being related to correction processing of a prediction image of the processed block; registers, in a prediction candidate list for a merge mode, one or more prediction candidates each being a combination of MV information and correction processing information, the prediction candidates including a prediction candidate which is a combination of the motion vector information and the correction processing information stored in the FIFO buffer; and selects a prediction candidate from the prediction candidate list when a current block is to be processed in the merge mode, and performs correction processing of a prediction image of the current block, based on the correction processing information.