公开(公告)号：US5937325A

公开(公告)日：1999-08-10

申请号：US966306

申请日：1997-11-07

Applicant: Emi Ishida

Inventor： Emi Ishida

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/268

CPC classification number: H01L29/665 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/4941 ,  H01L29/66507

Abstract: A method of forming a titanium silicide (69) includes the steps of forming a transistor having a source region (58), a drain region (60) and a gate structure (56) and forming a titanium layer (66) over the transistor. A first anneal is performed with a laser anneal at an energy level that causes the titanium layer (66) to react with the gate structure (56) to form a high resistivity titanium silicide phase (68) having substantially small grain sizes. The unreacted portions of the titanium layer (66) are removed and a second anneal is performed, thereby causing the high resistivity titanium silicide phase (68) to convert to a low resistivity titanium silicide phase (69). The small grain sizes obtained by the first anneal allow low resistivity titanium silicide phase (69) to be achieved at device geometries less than about 0.25 micron.

Abstract translation: 形成硅化钛（69）的方法包括以下步骤：形成具有源极区（58），漏极区（60）和栅极结构（56）并在晶体管上形成钛层（66）的晶体管。 以能量水平进行激光退火来执行第一退火，该能级导致钛层（66）与栅极结构（56）反应以形成具有基本上小的晶粒尺寸的高电阻率硅化钛相（68）。 除去钛层（66）的未反应部分，进行第二退火，从而使高电阻率钛硅化物相（68）转化为低电阻率硅化钛相（69）。 通过第一退火获得的小晶粒尺寸允许在小于约0.25微米的器件几何形状下实现低电阻率硅化钛相（69）。