公开(公告)号：US07298189B2

公开(公告)日：2007-11-20

申请号：US10965985

申请日：2004-10-15

申请人： Yong Gu Kang ,  Jun Hyun Chun

发明人： Yong Gu Kang ,  Jun Hyun Chun

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： The DLL circuit detects a frequency of an external clock signal and adjusts a coarse delay during a DLL circuit operation, thereby quickly terminating a feedback operation of the DLL circuit and having a reduced circuit area of a delay line. Therefore, the DLL circuit can be used for next generation high-integration and high-frequency memory devices such as DDR2 SDRAMs.

摘要翻译： DLL电路检测外部时钟信号的频率，并且在DLL电路操作期间调整粗略的延迟，从而快速地终止DLL电路的反馈操作并且具有减小的延迟线的电路面积。 因此，DLL电路可用于下一代高集成度和高​​频存储器件，如DDR2 SDRAM。

公开(公告)号：US20070258299A1

公开(公告)日：2007-11-08

申请号：US11641854

申请日：2006-12-20

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/26 ,  G11C7/02 ,  G11C29/12 ,  G11C29/50 ,  G11C2029/5002

摘要： Disclosed are a semiconductor memory apparatus and a method of testing the same. The semiconductor memory apparatus includes memory banks, each of which includes a plurality of memory cells, a peripheral circuit unit that includes a plurality of circuit groups around the memory banks, and a noise generating block that is disposed in the peripheral circuit unit and selectively applies a noise to the memory banks in a test mode.

摘要翻译： 公开了一种半导体存储装置及其测试方法。 半导体存储装置包括存储体，每个存储体包括多个存储单元，包括存储体周围的多个电路组的外围电路单元，和设置在外围电路单元中的选择性地应用的噪声发生模块 在测试模式下对记忆体的噪声。

公开(公告)号：US07142028B2

公开(公告)日：2006-11-28

申请号：US10879183

申请日：2004-06-30

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A clock duty ratio correction circuit corrects a duty ratio of internal clock signals at 1:1. The clock duty ratio correction circuit comprises a clock buffer unit, a charge pump unit, a comparison control unit, a voltage comparison unit, a counter and a D/A converter. The clock duty ratio correction circuit converts a differential internal clock signal into a voltage level corresponding to the pulse width of the differential internal clock signal, and compares the voltage level to generate a count signal. Additionally, the clock duty ratio correction circuit divides a reference voltage at a predetermined ratio in response to the count signal to generate a duty ratio correcting signal, and corrects the duty ratio of the differential internal clock signal by using the voltage level difference of the duty ratio correcting signal.

摘要翻译： 时钟占空比校正电路以1：1校正内部时钟信号的占空比。 时钟占空比校正电路包括时钟缓冲器单元，电荷泵单元，比较控制单元，电压比较单元，计数器和D / A转换器。 时钟占空比校正电路将差分内部时钟信号转换成与差分内部时钟信号的脉冲宽度相对应的电压电平，并比较电压电平以产生计数信号。 此外，时钟占空比校正电路响应于计数信号以预定比例对参考电压进行分压以产生占空比校正信号，并且通过使用占空比的电压电平差校正差分内部时钟信号的占空比 比率校正信号。

公开(公告)号：US20060220728A1

公开(公告)日：2006-10-05

申请号：US11174506

申请日：2005-07-06

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M1/088

摘要： The present invention provides a voltage booster circuit for effectively supplying a boosted voltage of a stable level despite of small area. The voltage booster circuit of the present invention includes: an oscillator for generating a basic pulse signal; a phase divider for dividing a frequency of the basic pulse signal to output a plurality of pulse signals having predetermined phase difference; a first to a fourth charge pumps for outputting a boosted voltage in response to a correspondent pulse signal among the plurality of pulse signals; and a drive controller for controlling the oscillator to maintain the boosted voltage to have a desired level.

摘要翻译： 本发明提供了一种用于有效地提供具有小面积的稳定电平的升压电压的升压电路。 本发明的升压电路包括：用于产生基本脉冲信号的振荡器; 分相器，用于分频基本脉冲信号的频率，以输出具有预定相位差的多个脉冲信号; 第一至第四电荷泵，用于响应于所述多个脉冲信号中的对应脉冲信号而输出升压电压; 以及驱动控制器，用于控制振荡器以保持升压电压具有期望的电平。

公开(公告)号：US5666074A

公开(公告)日：1997-09-09

申请号：US648276

申请日：1996-05-15

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/06 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G01R19/00

CPC分类号： G11C5/14 ,  G11C7/06

摘要： A sense amplifier power supply circuit for supplying a power source to a sense amplifier of a semiconductor memory device having two or more memory cell blocks is disclosed including a first power closed circuit for connecting a first power voltage line to a second ground voltage line, a second power closed circuit for connecting a first ground voltage line to a second power voltage line, a first switching transistor for supplying a power voltage to the first power closed circuit, a second switching transistor for supplying a ground voltage to the second power closed circuit, a third switching transistor for supplying the power voltage to the second power closed circuit, and a fourth switching transistor for supplying the ground voltage line to the first power closed circuit. The first power voltage and the first ground voltage line respectively supply the power voltage and the ground voltage to operate sense amplifiers of a first memory cell array; the second power voltage line and the second ground voltage line respectively supply the power voltage and the ground voltage to operate the sense amplifiers of a second memory cell array.

摘要翻译： 公开了一种用于向具有两个或多个存储单元块的半导体存储器件的读出放大器提供电源的读出放大器电源电路，其包括用于将第一电源电压线连接到第二接地电压线的第一电源闭合电路， 用于将第一接地电压线连接到第二电源线的第二功率闭合电路，用于向第一功率闭合电路提供电源电压的第一开关晶体管，用于向第二功率闭合电路提供接地电压的第二开关晶体管， 用于向第二功率闭合电路提供电源电压的第三开关晶体管和用于将接地电压线提供给第一功率闭合电路的第四开关晶体管。 第一电源电压和第一接地电压线分别提供电源电压和地电压以操作第一存储单元阵列的读出放大器; 第二电源线和第二接地电压线分别提供电源电压和接地电压，以操作第二存储单元阵列的读出放大器。