公开(公告)号：US08305833B2

公开(公告)日：2012-11-06

申请号：US11809244

申请日：2007-05-30

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G11C8/00

CPC分类号： G11C5/025 ,  G11C8/12 ,  G11C2207/105

摘要： A semiconductor memory device having semiconductor memory chips, each semiconductor memory chip includes a plurality of memory banks capable of independently to be accessed, each memory bank having a plurality of memory blocks, wherein at least two memory blocks, which are neighbored each other in the same memory bank, have the different number of unit memory blocks, so that each bank has a non-rectangular shape.

摘要翻译： 一种具有半导体存储器芯片的半导体存储器件，每个半导体存储器芯片包括能够独立地被访问的多个存储器组，每个存储体具有多个存储器块，其中至少两个存储块彼此相邻 相同的存储体，具有不同数量的单位存储块，使得每个存储体具有非矩形形状。

公开(公告)号：US20110181328A1

公开(公告)日：2011-07-28

申请号：US13083247

申请日：2011-04-08

申请人： Kwang Jun CHO ,  Jun Hyun Chun

发明人： Kwang Jun CHO ,  Jun Hyun Chun

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal.

摘要翻译： 一种频率调整装置，包括：频率控制信号生成部，其响应于基准时钟信号，生成逐位变化的多位频率控制信号;以及频率调整部，其调整基准的频率 响应于多位频率控制信号的时钟信号。

公开(公告)号：US07937629B2

公开(公告)日：2011-05-03

申请号：US11641854

申请日：2006-12-20

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G11C29/00 ,  G11C7/00 ,  G01R35/00 ,  G01R31/26

CPC分类号： G11C29/26 ,  G11C7/02 ,  G11C29/12 ,  G11C29/50 ,  G11C2029/5002

摘要： Disclosed are a semiconductor memory apparatus and a method of testing the same. The semiconductor memory apparatus includes memory banks, each of which includes a plurality of memory cells, a peripheral circuit unit that includes a plurality of circuit groups around the memory banks, and a noise generating block that is disposed in the peripheral circuit unit and selectively applies a noise to the memory banks in a test mode.

摘要翻译： 公开了一种半导体存储装置及其测试方法。 半导体存储装置包括存储体，每个存储体包括多个存储单元，包括存储体周围的多个电路组的外围电路单元，和设置在外围电路单元中的选择性地应用的噪声发生模块 在测试模式下对记忆体的噪声。

公开(公告)号：US07564254B2

公开(公告)日：2009-07-21

申请号：US11647147

申请日：2006-12-29

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R31/26

CPC分类号： G01R31/318335 ,  G01R31/31712 ,  G01R31/31724 ,  G01R31/318511

摘要： A semiconductor device includes: a command control circuit for decoding a command signal to output a test signal and a normal control signal; a normal circuit for performing a predetermined operation in response to the normal control signal; and a test circuit for testing electrical characteristics of unit elements provided in the normal circuit in response to the test signal.

摘要翻译： 半导体器件包括：命令控制电路，用于解码命令信号以输出测试信号和正常控制信号; 用于响应于正常控制信号执行预定操作的正常电路; 以及用于测试响应于测试信号在普通电路中提供的单元的电特性的测试电路。

公开(公告)号：US07537942B2

公开(公告)日：2009-05-26

申请号：US11685870

申请日：2007-03-14

申请人： Kang Youl Lee ,  Jun Hyun Chun

发明人： Kang Youl Lee ,  Jun Hyun Chun

IPC分类号： H01L21/66

CPC分类号： H03K19/017581

摘要： Provided is a method of changing an output current value of an off-chip driver by means of a counting circuit including pluralities of fuses for controlling the off-chip driver, that includes measuring the output current value of the off-chip driver after completing a wafer test; cutting the fuses of the counting circuit off when the measured output current value is smaller than a target value, increasing the initial value of a off-chip driving control signal; and fabricating a package when the measured output current value is equal to a target value.

摘要翻译： 提供了一种通过包括用于控制片外驱动器的多个保险丝的计数电路来改变片外驱动器的输出电流值的方法，其包括在完成了片外驱动器之后测量片外驱动器的输出电流值 晶圆试验; 当测量的输出电流值小于目标值时，切断计数电路的熔丝，增加芯片外驱动控制信号的初始值; 以及当测量的输出电流值等于目标值时制造封装。

公开(公告)号：US20060220683A1

公开(公告)日：2006-10-05

申请号：US11176394

申请日：2005-07-08

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： H03K19/0175

CPC分类号： H03K17/164

摘要： Provided is a semiconductor memory device that is capable of internally controlling a strength of an output driver. The semiconductor memory device includes: an OCD (off chip driver) control signal generator for decoding EMRS and addresses to generate a plurality of external strength control signals or an internal driving signal; a self control signal generator for detecting a level of a driving voltage to generate a plurality of internal strength control signals in response to the internal driving signal; a control signal generator for generating a strength control signal in response to the external strength control signals or the internal strength control signals; and a data output driver for outputting data, the strength of the data output driver being controlled according to the strength control signal.

摘要翻译： 提供了能够内部控制输出驱动器的强度的半导体存储器件。 半导体存储器件包括：用于解码EMRS的OCD（片外驱动器）控制信号发生器和用于产生多个外部强度控制信号或内部驱动信号的地址; 自动控制信号发生器，用于响应于内部驱动信号，检测驱动电压的电平以产生多个内部强度控制信号; 控制信号发生器，用于响应于外部强度控制信号或内部强度控制信号产生强度控制信号; 以及用于输出数据的数据输出驱动器，根据强度控制信号控制数据输出驱动器的强度。

公开(公告)号：US06643218B1

公开(公告)日：2003-11-04

申请号：US10347276

申请日：2003-01-21

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： G11C800

CPC分类号： G11C7/12

摘要： A semiconductor memory device generates a precharge control signal asynchronous from a dock signal. The semiconductor memory device includes a memory cell array for storing data, and a precharge control signal generator for generating a precharge control signal in a test mode, by employing a predetermined control signal which does not influence access to the data stored in the memory cell array, even when maintained in a high or low level in the test mode. The precharge control signal generator receives the control signal, outputs a signal having an identical state to the control signal in the normal mode, and also outputs a signal fixed in a high or low level in the test mode. As a result, it is possible to generate the precharge control signal which does not require a delay time as long as a command hold time.

摘要翻译： 半导体存储器件从停靠信号产生异步的预充电控制信号。 半导体存储器件包括用于存储数据的存储单元阵列和预充电控制信号发生器，用于通过采用不影响对存储在存储单元阵列中的数据的访问的预定控制信号来产生测试模式中的预充电控制信号 即使在测试模式下保持在高或低电平。 预充电控制信号发生器接收控制信号，在正常模式下输出与控制信号具有相同状态的信号，并且还在测试模式下输出固定在高电平或低电平的信号。 结果，可以产生不需要延迟时间的预充电控制信号，只要指令保持时间即可。

公开(公告)号：US06532184B2

公开(公告)日：2003-03-11

申请号：US09994652

申请日：2001-11-28

申请人： Jun Hyun Chun

发明人： Jun Hyun Chun

IPC分类号： G11C700

CPC分类号： G11C7/12

摘要： A semiconductor memory device generates a precharge control signal asynchronous from a clock signal. The semiconductor memory device includes a memory cell array for storing data, and a precharge control signal generator for generating a precharge control signal in a test mode, by employing a predetermined control signal which does not influence access to the data stored in the memory cell array, even when maintained in a high or low level in the test mode. The precharge control signal generator receives the control signal, outputs a signal having an identical state to the control signal in the normal mode, and also outputs a signal fixed in a high or low level in the test mode. As a result, it is possible to generate the precharge control signal which does not require a delay time as long as a command hold time.

公开(公告)号：US20130156126A1

公开(公告)日：2013-06-20

申请号：US13590282

申请日：2012-08-21

申请人： Jin Il CHUNG ,  Jun Hyun CHUN ,  Jin Wook BURM ,  Dae Ho YUN

发明人： Jin Il CHUNG ,  Jun Hyun CHUN ,  Jin Wook BURM ,  Dae Ho YUN

IPC分类号： H03K5/22 ,  H04L27/02 ,  H04L27/06

CPC分类号： H03K5/249 ,  H04L25/4917 ,  H04L27/06

摘要： A rail-to-rail comparator including a first comparison unit connected to a first terminal and configured to compare differential input signals to differential reference voltages; a second comparison unit connected to a second terminal and configured to compare the differential input signals to the differential reference voltages; and an output unit configured to be driven in response to a clock signal and to generate a complementary output signal according to comparison results of the first and second comparison units.

摘要翻译： 一种轨到轨比较器，包括连接到第一端子并被配置为将差分输入信号与差分参考电压进行比较的第一比较单元; 第二比较单元，连接到第二端子并且被配置为将差分输入信号与差分参考电压进行比较; 以及输出单元，被配置为响应于时钟信号被驱动，并且根据第一和第二比较单元的比较结果产生互补的输出信号。

公开(公告)号：US07916565B2

公开(公告)日：2011-03-29

申请号：US12172949

申请日：2008-07-14

申请人： Jun-Hyun Chun

发明人： Jun-Hyun Chun

IPC分类号： G11C7/00

CPC分类号： G11C29/12 ,  G11C29/48

摘要： A semiconductor memory device including a test circuit capable of reducing test time includes a test circuit for generating leakage current in the semiconductor memory device in a standby state in response to a test mode signal and a standby signal that provides standby state information of the semiconductor memory device.

摘要翻译： 包括能够减少测试时间的测试电路的半导体存储器件包括用于响应于测试模式信号和提供半导体存储器的备用状态信息的待机信号在待机状态下产生半导体存储器件中的漏电流的测试电路 设备。