Abstract:
The invention provides techniques for secure messages transmission using a public key system to exchange secret keys. A first entity creates public and private keys by generating a product n of two large, randomly chosen prime numbers, and then generating random matrices {A, C}, in the group GL(r,Zn) with a chosen matrix rank r such that AC is not equal to CA, and then generating a matrix B=CAC, and finding a matrix G that commutes with C. Matrices A, B, G and the integers n and r are then published as the public key and matrix C is then kept as the private key. A second entity then obtains the public key and calculates a secret matrix D that commutes with G, and further calculates the matrices K=DBD and E=DAD. The message to be sent is then encrypted using matrix K as the secret key and then sent to the first entity with matrix E. First entity then retrieves secret matrix K using K=CEC and then decrypts the received encrypted message using the retrieved secret matrix K.
Abstract:
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one register for storing access information to access at least one array stored in the plurality of memory cells. According to another aspect, an electronic system is provided that includes a main memory, a dynamic array cache memory device, a general cache memory device, and a processor. The dynamic array cache memory device is coupled to the main memory and adapted for caching array data. The general cache memory device is coupled to the main memory and is adapted for caching regular data. The processor is coupled to and adapted for communication with the main memory, the general cache memory device, and the dynamic array cache memory device.
Abstract:
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic overlays. According to one embodiment, the device includes a plurality of memory cells and at least one register for storing access information to access at least one array stored in the plurality of memory cells. According to another aspect, an electronic system is provided that includes a main memory, a dynamic array cache memory device, a general cache memory device, and a processor. The dynamic array cache memory device is coupled to the main memory and adapted for caching array data. The general cache memory device is coupled to the main memory and is adapted for caching regular data. The processor is coupled to and adapted for communication with the main memory, the general cache memory device, and the dynamic array cache memory device.
Abstract:
A resampling system and method for producing a resampled destination image from a source image by solving coefficients for a cubic polynomial transition model between first and second adjacent source pixels from the sample values of the first and second samples and approximations of the first and second sample gradients at the first and second samples, respectively. Approximations of the first and second color gradients are based on a multiple of first and second color slopes, such as twice the value of the color slope. The first color slope is calculated from the sample values of a previous pixel and the first sample and the second sample slope is calculated from the sample values of a subsequent sample and the second sample. The resulting gradient approximations and sample values are used in the cubic transition model to calculate an output sample value for rendering a resampled destination image.
Abstract:
A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row resampling circuit calculates row output values which are provided to a column resampling circuit that calculates output sample values therefrom. The column resampling circuit includes a shift register that receives the row output values and shifts the row output values through the shift register as the row output samples are calculated. The shift register has a plurality of evenly spaced sample output terminals from which the row output values are sampled by an interpolation circuit for calculation of the output sample values.
Abstract:
An improved FIR filter based upon squaring is used to self-determine a filter constant equal to the sum-of-squares of the filter coefficients. An input signal is forced to zero for T samples, where T is the number of accumulator cells in an accumulator stage, and at the end of such zero samples the output from the filter is latched as the filter constant for use in filtering the normal input signal. The FIR filter may also be placed in a co-processor mode, using a FIFO register between the input of the FIR filter and a processor bus. A CPU on the bus initiates the co-processor mode and loads data into the FIFO. When the FIFO has data the data is read out and input to the FIR filter. The output of the FIR filter is placed on the processor bus. To determine the values of the filter coefficients loaded in the FIR filter, the data loaded by the CPU is an impulse signal having T−1 zero samples before and after an impulse sample, the output for each sample representing one of the filter coefficients.
Abstract:
Block matching for picture motion estimation uses Gray codes, and preferably a new Hamming-2 Gray code where the bit pattern changes by only one bit for each step in the Gray code count sequence with the additional condition that all other codes are at least two bits different if not adjacent in the count sequence. The pixels for a reference block from a first picture frame and the pixels for a corresponding block within a search area of the next picture frame are each quantized and then converted to an appropriate Gray code. The Gray codes for corresponding pixels are compared to determine whether they are equal or adjacent to each other. If there is adjacency or equality a match signal is generated for that pixel which is tallied. The total tally for each reference block position within the search area is determined, with the maximum tally indicating a match between blocks from which picture motion estimation may be determined.
Abstract:
A FIR filter based upon squaring accumulates the sum of the squares of the samples of a digital input signal. The samples also are added to respective filter coefficients, squared and accumulated in a plurality of filter stages. The sum of the squares of the samples are subtracted, together with a constant that is the sum of the squares of the filter coefficients, from the output of the last filter stage to produce an output signal that is divided by two to produce the samples for a digital output signal.
Abstract:
A method for locking scales to a waveform display uses reference points from the waveform to determine starting scale points. Based upon the starting scale points and the characteristics of the waveform the scales are calculated. Any changes in gain in the waveform are applied to the scales so that the scales change in direct proportion to the waveform. The field/line numbers of a television video signal are tracked and displayed on the waveform display to identify that portion of the waveform relative to a picture frame which is being displayed.