Enabling flash cell scaling by shaping of the floating gate using spacers
    41.
    发明申请
    Enabling flash cell scaling by shaping of the floating gate using spacers 审中-公开
    通过使用间隔件对浮动栅极进行整形来启用闪存单元缩放

    公开(公告)号:US20080237680A1

    公开(公告)日:2008-10-02

    申请号:US11728829

    申请日:2007-03-27

    IPC分类号: H01L29/788 H01L21/336

    摘要: According to embodiments of the invention, an inverted “T” shaped gate can be formed for transistor flash memory cells to reduce feature sizes, to reduce pitch size, to increase gate coupling ratio and/or to reduce parasitic capacitive effects between adjacent flash cells or cell floating gates, such as with optimization of control gate distance between field gates. Such feature sizes include channel width; isolation region width; width of a portion of a gate electrode and/or half-pitch distance between adjacent cells or rows of transistors (e.g., cells).

    摘要翻译: 根据本发明的实施例,可以为晶体管闪存单元形成反向“T”形栅极,以减小特征尺寸,减小间距尺寸,增加栅极耦合比和/或减小相邻闪存单元之间的寄生电容效应,或 单元浮栅,例如优化场门之间的控制栅距。 这些特征尺寸包括通道宽度; 隔离区宽度; 栅电极的一部分的宽度和/或相邻单元或行晶体管(例如,单元)之间的半间距距离。

    Dual trench isolation using single critical lithographic patterning
    42.
    发明授权
    Dual trench isolation using single critical lithographic patterning 失效
    使用单重临界光刻图案的双沟槽隔离

    公开(公告)号:US06949801B2

    公开(公告)日:2005-09-27

    申请号:US10669825

    申请日:2003-09-23

    IPC分类号: H01L21/762 H01L29/76

    CPC分类号: H01L21/76229

    摘要: A method and apparatus for forming shallow and deep isolation trenches in a substrate so that the shallow and deep isolation trenches are aligned without mis-registration. The method includes forming a plurality of shallow trenches, covering a portion of the plurality of shallow trenches, then etching the uncovered shallow trenches to create deeper trenches.

    摘要翻译: 一种用于在衬底中形成浅和深隔离沟槽的方法和装置,使得浅和深隔离沟槽被对准而不被错配。 该方法包括形成多个浅沟槽,覆盖多个浅沟槽的一部分,然后蚀刻未覆盖的浅沟槽以产生更深的沟槽。