摘要:
According to embodiments of the invention, an inverted “T” shaped gate can be formed for transistor flash memory cells to reduce feature sizes, to reduce pitch size, to increase gate coupling ratio and/or to reduce parasitic capacitive effects between adjacent flash cells or cell floating gates, such as with optimization of control gate distance between field gates. Such feature sizes include channel width; isolation region width; width of a portion of a gate electrode and/or half-pitch distance between adjacent cells or rows of transistors (e.g., cells).
摘要:
A method and apparatus for forming shallow and deep isolation trenches in a substrate so that the shallow and deep isolation trenches are aligned without mis-registration. The method includes forming a plurality of shallow trenches, covering a portion of the plurality of shallow trenches, then etching the uncovered shallow trenches to create deeper trenches.
摘要:
A method and apparatus for forming shallow and deep isolation trenches in a substrate so that the shallow and deep isolation trenches are aligned without mis-registration. The method includes forming a plurality of shallow trenches, covering a portion of the plurality of shallow trenches, then etching the uncovered shallow trenches to create deeper trenches.