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    Boosting seed voltage for a memory device
    2.
    发明授权
    Boosting seed voltage for a memory device 有权
    提升存储器件的种子电压

    公开(公告)号：US07835187B2

    公开(公告)日：2010-11-16

    申请号：US12262410

    申请日：2008-10-31

    Applicant: Satoru Tamada ,  Neal R Mielke ,  Krishna Parat

    Inventor： Satoru Tamada ,  Neal R Mielke ,  Krishna Parat

    IPC: G11C11/34

    CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C16/3427

    Abstract: A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.

    Abstract translation: 提供了一种使用相邻位线之间的位线位线电容来提高存储器件中的种子电压的方法和装置。 该方法可以包括预充电阶段，升压阶段，均衡阶段和同相锁定。 在一个实施例中，该方法可以包括两次提升种子电压。 位线可以分为一个或多个段。

    FLOATING GATE STRUCTURES
    3.
    发明申请
    FLOATING GATE STRUCTURES 有权
    浮动门结构

    公开(公告)号：US20090283817A1

    公开(公告)日：2009-11-19

    申请号：US12165272

    申请日：2008-06-30

    Applicant: Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

    Inventor： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

    IPC: H01L29/788 ,  H01L21/28

    CPC classification number: H01L21/28052 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

    Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

    Abstract translation: 通常描述浮栅结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率 以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率 。 与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

    NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC
    4.
    发明申请
    NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC 审中-公开
    具有多层阻塞介质的非易失性存储单元

    公开(公告)号：US20090001443A1

    公开(公告)日：2009-01-01

    申请号：US11771482

    申请日：2007-06-29

    Applicant: Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Rhett T. Brewer ,  Thomas M. Graettinger ,  Nirmal Ramaswamy ,  M. Noel Rocklein

    Inventor： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Rhett T. Brewer ,  Thomas M. Graettinger ,  Nirmal Ramaswamy ,  M. Noel Rocklein

    IPC: H01L29/788

    CPC classification number: H01L29/513 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234

    Abstract: Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.

    Abstract translation: 公开了一种非易失性存储单元。 非易失性存储单元包括具有有源区的基板。 底部电介质层设置在衬底的有源区上方，其向电荷载流子提供隧道迁移到有源区。 电荷存储节点设置在底部电介质层的上方。 此外，非易失性存储单元包括设置在电荷存储节点上方的多个顶部电介质层。 多个顶部电介质层中的每一个可以用一组属性进行调谐，以减少穿过多个顶部电介质层的漏电流。 在多个顶部电介质层中，设置有控制栅极。

    Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the method
    5.
    发明授权
    Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the method 有权
    使用牺牲柱间隔物和根据该方法形成的非易失性存储单元形成非易失性存储单元的方法

    公开(公告)号：US07183162B1

    公开(公告)日：2007-02-27

    申请号：US11284982

    申请日：2005-11-21

    Applicant: Steven R. Soss ,  Krishna Parat

    Inventor： Steven R. Soss ,  Krishna Parat

    IPC: H01L21/8247

    CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A method of forming a microelectronic non-volatile memory cell, a memory cell formed according to the method, and a system including the memory cell. The method comprises: providing a substrate; providing a pair of spaced apart isolation bodies on the substrate, the isolation bodies including respective raised isolation portions, providing the pair comprising providing a buffer layer on the substrate; providing pillar spacers on side walls of the raised isolation portions; removing the buffer layer after providing the pillar spacers; removing the pillar spacers during removing the buffer layer; providing a tunnel dielectric on the surface of the substrate after removing the buffer layer; providing a floating gate on the tunnel dielectric; reducing a height of the isolation bodies to yield corresponding isolation regions; providing source and drain regions on opposite sides of the floating gate; providing an interpoly dielectric on the floating gate; and providing a control gate on the interpoly dielectric to yield the memory cell.

    Abstract translation: 形成微电子非易失性存储单元的方法，根据该方法形成的存储单元和包括存储单元的系统。 该方法包括：提供衬底; 在所述衬底上提供一对间隔开的隔离体，所述隔离体包括相应的凸起隔离部分，提供所述对，包括在所述衬底上提供缓冲层; 在凸起隔离部分的侧壁上提供柱状间隔物; 在提供柱间隔物之后去除缓冲层; 在移除缓冲层期间移除柱状间隔物; 在去除缓冲层之后在衬底的表面上提供隧道电介质; 在隧道电介质上提供浮动栅极; 降低隔离体的高度以产生相应的隔离区; 在浮动栅极的相对侧上提供源极和漏极区域; 在所述浮动栅极上提供互补电介质; 以及在所述互聚电介质上提供控制栅极以产生所述存储单元。

    Memory devices and programming memory arrays thereof
    7.
    发明授权
    Memory devices and programming memory arrays thereof 有权
    存储器件及其编程存储器阵列

    公开(公告)号：US09171626B2

    公开(公告)日：2015-10-27

    申请号：US13561637

    申请日：2012-07-30

    Applicant: Akira Goda ,  Haitao Liu ,  Krishna Parat

    Inventor： Akira Goda ,  Haitao Liu ,  Krishna Parat

    IPC: G11C16/04 ,  G11C16/10 ,  H01L27/115

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11582

    Abstract: An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.

    Abstract translation: 一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到 数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压 之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。

    MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF
    8.
    发明申请
    MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF 有权
    存储器件和编程存储器阵列

    公开(公告)号：US20140029345A1

    公开(公告)日：2014-01-30

    申请号：US13561637

    申请日：2012-07-30

    Applicant: Akira Goda ,  Haitao Liu ,  Krishna Parat

    Inventor： Akira Goda ,  Haitao Liu ,  Krishna Parat

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11582

    Abstract: An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.

    Abstract translation: 一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到 数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压 之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。

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