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公开(公告)号：US20250096956A1
公开(公告)日：2025-03-20
申请号：US18469387
申请日：2023-09-18
Applicant: QUALCOMM Incorporated
Inventor： Norberto AMAYA GONZALEZ , Luis MUNOZ LOZA , Sameh GUIRGUIS
Abstract: Certain aspects of the present disclosure provide techniques for periodic, frequency domain dependent block error rate (BLER) detection and correction. An example method, performed at a first wireless node, generally includes identifying differences in BLER for different resources used for transmissions between the first wireless node and a second wireless node, and performing one or more actions to mitigate an impact of the identified differences in BLER on subsequent transmissions between the first wireless node and a second wireless node.
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公开(公告)号：US20250096947A1
公开(公告)日：2025-03-20
申请号：US18467623
申请日：2023-09-14
Applicant: QUALCOMM Incorporated
Inventor： Hua WANG , Junyi LI , Tianyang BAI
IPC: H04L1/1812 , H04L5/00 , H04W72/232 , H04W76/20
Abstract: A method of wireless communication by a user equipment (UE) includes transmitting, to a network node, a first stage hybrid automatic repeat request acknowledgement (HARQ-ACK) codebook on an orthogonal multiple access (OMA) resource. The method also includes transmitting, to the network node, a second stage HARQ-ACK codebook on a non-orthogonal multiple access (NOMA) resource in response to the first stage HARQ-ACK codebook indicating at least one negative acknowledgement (NACK).
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公开(公告)号：US20250096933A1
公开(公告)日：2025-03-20
申请号：US18967523
申请日：2024-12-03
Applicant: QUALCOMM Incorporated
Inventor： Sanghoon KIM , Alexei Yurievitch GOROKHOV , Hari SANKAR
IPC: H04L1/00 , H04W72/0446 , H04W72/21
Abstract: Methods, apparatuses, and computer-readable storage medium for rate matching for TBoMS are provided. An example method includes calculating a slot length for each UL slot of a plurality of UL slots, the slot length for each UL slot being associated with a plurality of rate matching output bits, each UL slot including a starting point for the plurality of rate matching output bits, the slot length for each UL slot being associated with a starting boundary, the plurality of UL slots being associated with at least one of a single TB or a single rate matching. The example method may include allocating one or more bits of the plurality of rate matching output bits for a modulation process. The example method may include refraining allocating at least one bit of the plurality of rate matching output bits for the modulation process, the at least one bit corresponding to UCI multiplexing.
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44.发明申请公开(公告)号：US20250096932A1
公开(公告)日：2025-03-20
申请号：US18658764
申请日：2024-05-08
Applicant: QUALCOMM Incorporated
Inventor： Jialing Li CHEN , Kanke WU , Sameer VERMANI , Bin TIAN , Youhan KIM , Qifan CHEN
Abstract: This disclosure provides methods, components, devices and systems for managing long low-density parity check (LDPC) codewords in ultra high reliability (UHR) systems. One method for wireless communication may be performable at a transmitter device or node. The method may include transmitting signaling to a receiver device or node indicating that the transmitter device supports use of a first LDPC codeword length that is greater than or equal to a threshold LDPC codeword length. The method may further include transmitting an LDPC codeword of the first LDPC codeword length (e.g., a long LDPC codeword) to the receiver device when one or more conditions are satisfied.
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45.发明申请公开(公告)号：US20250096929A1
公开(公告)日：2025-03-20
申请号：US18415437
申请日：2024-01-17
Applicant: QUALCOMM Incorporated
Inventor： Kanke WU , Sameer VERMANI , Bin TIAN
Abstract: This disclosure provides methods, components, devices and systems for managing long low-density parity check (LDPC) codewords in ultra high reliability (UHR) systems. One method for wireless communication may be performable at a transmitter device or node. The method may include transmitting signaling to a receiver device or node indicating that the transmitter device supports use of a first LDPC codeword length that is greater than or equal to a threshold LDPC codeword length. The method may further include transmitting an LDPC codeword of the first LDPC codeword length (e.g., a long LDPC codeword) to the receiver device when one or more conditions are satisfied.
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Patent Agency Ranking
公开(公告)号：US20250096839A1
公开(公告)日：2025-03-20
申请号：US18470245
申请日：2023-09-19
Applicant: Qualcomm Incorporated
Inventor： Waqas Ahmad , Chinmaya Mishra
Abstract: An apparatus is disclosed for oscillator leakage calibration. In example aspects, the apparatus includes a mixer circuit and calibration circuitry. The mixer circuit has a first stage including at least one transistor coupled between a mixer input and a mixer output and a second stage including one or more transistors coupled between the at least one transistor and the mixer output. The mixer circuit also has tuning circuitry coupled to the at least one transistor. The calibration circuitry includes at least one resistor coupled between a power distribution node and at least one mixer node, with the at least one mixer node coupled between the at least one transistor and the one or more transistors, and at least one switch coupled between the power distribution node and the at least one mixer node. The calibration circuitry also includes controller circuitry coupled between the mixer node and the tuning circuitry.
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公开(公告)号：US20250096747A1
公开(公告)日：2025-03-20
申请号：US18470039
申请日：2023-09-19
Applicant: QUALCOMM INCORPORATED
Inventor： Laya MOHAMMADI , Chirag Dipak PATEL , Chuan WANG , Bhushan Shanti ASURI
Abstract: A phase shifter having an input matching network, a vector modulator connected to the input matching network, the vector modulator configured to alter an amplitude of signals provided by the input matching network, bias networks coupled to outputs of the vector modulator, and a combining circuit connected to the outputs of the vector modulator, the combining circuit configured to generate a first phase (θ1) signal from the outputs of the vector modulator.
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公开(公告)号：US20250096742A1
公开(公告)日：2025-03-20
申请号：US18470139
申请日：2023-09-19
Applicant: Qualcomm Incorporated
Inventor： Lei Ma
Abstract: An apparatus is disclosed for implementing a clamping circuit with an interstage matching network or between two amplifier stages to provide power clamping. In example aspects, the apparatus includes an amplifier circuit having an input port and an output port. The amplifier circuit includes a driver amplifier, an interstage matching network, a power amplifier, and a clamping circuit. The driver amplifier includes a driver amplifier output and is coupled between the input port and the output port. The power amplifier includes a power amplifier input and is coupled between the driver amplifier output and the output port. The interstage matching network is coupled between the driver amplifier output and the power amplifier input. The clamping circuit includes a transistor and a resistor coupled thereto. The clamping circuit is coupled to the interstage matching network via a node that is coupled between the driver amplifier output and the power amplifier input.
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公开(公告)号：US20250096737A1
公开(公告)日：2025-03-20
申请号：US18470310
申请日：2023-09-19
Applicant: QUALCOMM Incorporated
Inventor： Xingyi HUA , Hsiao-Tsung YEN , David Zixiang YANG , Mehmet UZUNKOL
Abstract: A low-noise amplifier (LNA) includes a first transistor, a first source inductor coupled to a source of the first transistor, and a second transistor, wherein a source of the second transistor is coupled to a drain of the first transistor, a gate of the second transistor is coupled to a bias circuit, and a drain of the second transistor is coupled to an output of the LNA. The LNA also includes an output inductor coupled between a supply rail and the output of the LNA, wherein the output inductor is magnetically coupled with the first source inductor.
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50.发明申请公开(公告)号：US20250096734A1
公开(公告)日：2025-03-20
申请号：US18471231
申请日：2023-09-20
Applicant: QUALCOMM Incorporated
Inventor： Sunbo SHIM , Guoxiang HAN , David Angel CALVILLO CORTES , Paolo Enrico DE FALCO , Antonino SCUDERI
Abstract: A phase-reconfigurable circuit for a dual-input power amplifier is provided. The circuit includes an envelope detector configured to process an envelope of an RF input signal into an envelope signal. A first vector-sum phase-shifter and a second vector-sum phase-shifter processes an in-phase and a quadrature-phase version of the RF input signal with the envelope signal to produce a first differential output signal having a dynamically-modulated phase difference with a second differential output signal.
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