公开(公告)号：US11334361B2

公开(公告)日：2022-05-17

申请号：US16806063

申请日：2020-03-02

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Joseph Michael Pusdesris ,  Muhammad Umar Farooq

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/30

Abstract: An apparatus has processing circuitry, and history storage circuitry to store local history records. Each local history record corresponds to a respective subset of instruction addresses and tracks a sequence of observed instruction behaviour observed for successive instances of instructions having addresses in that subset. Pointer storage circuitry to store a shared pointer shared between the local history records. The shared pointer indicates a common storage position reached in each local history record. Prediction circuitry determines predicted instruction behaviour for a given instruction address based on a selected portion of a selected local history record stored in the history storage circuitry. The prediction circuitry selects the selected local history record based on the given instruction address and selects the selected portion based on the shared pointer.

公开(公告)号：US11204773B2

公开(公告)日：2021-12-21

申请号：US16124247

申请日：2018-09-07

Applicant: Arm Limited

Inventor： William Elton Burky ,  Glen Andrew Harris ,  Yasuo Ishii

IPC: G06F9/38

Abstract: A data processing apparatus is provided. It includes processing circuitry for speculatively executing a plurality of instructions. Storage circuitry stores a current state of the processing circuitry and a plurality of previous states of the processing circuitry. Execution of the plurality of instructions changes the current state of the processing circuitry. Flush circuitry replaces, in response to a miss-prediction, the current state of the processing circuitry with a replacement one of the plurality of previous states of the processing circuitry.

公开(公告)号：US10963258B2

公开(公告)日：2021-03-30

申请号：US16155049

申请日：2018-10-09

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  Chris Abernathy

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus is provided that includes lookup circuitry to provide first prediction data in respect of a first block of instructions and second prediction data in respect of a second block of instructions. First processing circuitry provides a first control flow prediction in respect of the first block of instructions using the first prediction data and second processing circuitry provides a second control flow prediction in respect of the second block of instructions using the second prediction data. The first block of instructions and the second block of instructions collectively define a prediction block and the lookup circuitry uses a reference to the prediction block as at least part of an index to both the first prediction data and the second prediction data.

公开(公告)号：US10817298B2

公开(公告)日：2020-10-27

申请号：US15335741

申请日：2016-10-27

Applicant: ARM LIMITED

Inventor： Yasuo Ishii ,  Michael Filippo ,  Muhammad Umar Farooq

IPC: G06F9/38

Abstract: An apparatus comprises a branch target buffer (BTB) to store predicted target addresses of branch instructions. In response to a fetch block address identifying a fetch block comprising two or more program instructions, the BTB performs a lookup to identify whether it stores one or more predicted target addresses for one or more branch instructions in the fetch block. When the BTB is identified in the lookup as storing predicted target addresses for more than one branch instruction in said fetch block, branch target selecting circuitry selects a next fetch block address from among the multiple predicted target addresses returned in the lookup. A shortcut path bypassing the branch target selecting circuitry is provided to forward a predicted target address identified in the lookup as the next fetch block address when a predetermined condition is satisfied.