公开(公告)号：US12045620B2

公开(公告)日：2024-07-23

申请号：US17554573

申请日：2021-12-17

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  William Elton Burky ,  Michael Brian Schinzler ,  Jason Lee Setter ,  David Gum Lim

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3867

Abstract: A data processing apparatus is provided that comprises rename circuitry for performing a register rename stage of a pipeline in respect of a stream of operations. Move elimination circuitry performs a move elimination operation on the stream of operations in which a move operation is eliminated and the register rename stage performs an adjustment of an identity of registers in the stream of operations to compensate for the move operation being eliminated and demotion circuitry reverses or inhibits the adjustment in response to one or more conditions being met.

公开(公告)号：US12026515B2

公开(公告)日：2024-07-02

申请号：US17959556

申请日：2022-10-04

Applicant: Arm Limited

Inventor： William Elton Burky ,  Nicholas Andrew Plante ,  Alexander Cole Shulyak ,  Joshua David Knebel ,  Yasuo Ishii

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30181 ,  G06F9/3856

Abstract: A data processing apparatus includes detection circuitry that detects a parent instruction and a child instruction from a stream of instructions. The parent instruction references a destination register that is referenced as a source register by the child instruction. Adjustment circuitry then adjusts the child instruction to produce an adjusted child instruction whose behaviour is logically equivalent to a behaviour of executing the parent instruction followed by the child instruction.

公开(公告)号：US11977738B2

公开(公告)日：2024-05-07

申请号：US17903293

申请日：2022-09-06

Applicant: Arm Limited

Inventor： Abhishek Raja ,  Yasuo Ishii

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0673

Abstract: There is provided an apparatus, method and medium. The apparatus comprises a store buffer to store a plurality of store requests, where each of the plurality of store requests identifies a storage address and a data item to be transferred to storage beginning at the storage address, where the data item comprises a predetermined number of bytes. The apparatus is responsive to a memory access instruction indicating a store operation specifying storage of N data items, to determine an address allocation order of N consecutive store requests based on a copy direction hint indicative of whether the memory access instruction is one of a sequence of memory access instructions each identifying one of a sequence of sequentially decreasing addresses, and to allocate the N consecutive store requests to the store buffer in the address allocation order.

公开(公告)号：US11442863B2

公开(公告)日：2022-09-13

申请号：US17093792

申请日：2020-11-10

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Adrian Montero ,  Joseph Michael Pusdesris ,  Karthik Sundaram ,  Yasuo Ishii

IPC: G06F12/0862

Abstract: Data processing apparatuses and methods of processing data are disclosed. The operations comprise: storing copies of data items; and storing, in a producer pattern history table, a plurality of producer-consumer relationships, each defining an association between producer load indicator and a plurality of consumer load entries, each consumer load entry comprising a consumer load indicator and one or more usefulness metrics. Further steps comprise: initiating, in response to a data load from an address corresponding to the producer load indicator in the producer pattern history table and when at least one of the corresponding one or more usefulness meets a criterion, a producer prefetch of data to be prefetched for storing as a local copy; and issuing, when the data is returned, one or more consumer prefetches to return consumer data from a consumer address generated from the data returned by the producer prefetch and a consumer load indicator of a consumer load entry.

公开(公告)号：US11379239B2

公开(公告)日：2022-07-05

申请号：US16364557

申请日：2019-03-26

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry has a target prediction storage used to identify target addresses for instruction flow changing instructions that are predicted as taken. The target prediction storage comprises at least one entry that is configurable as a multi-taken entry to indicate that a source instruction flow changing instruction identified by that entry is a first instruction flow changing instruction with an associated first target address that identifies a series of instructions that is expected to exhibit static behaviour and that terminates with a second instruction flow changing instruction, where the second instruction flow changing instruction is unconditionally taken and has an associated second target address. The prediction circuitry is arranged, when making a prediction for a chosen instruction flow changing instruction that is identified by a multi-taken entry in the target prediction storage, to identify with reference to target address information stored in that multi-taken entry both the series of instructions and a target instruction at the second target address. It then causes the series of instructions and the target instruction to be identified in the fetch queue, and begins making further predictions starting from the target instruction at the second target address.

公开(公告)号：US11157284B1

公开(公告)日：2021-10-26

申请号：US16891431

申请日：2020-06-03

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  Joseph Michael Pusdesris

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus is described, comprising processing circuitry to speculatively execute an earlier instruction and a later instruction by generating a prediction of an outcome of the earlier instruction and a prediction of an outcome of the later instruction, wherein the prediction of the outcome of the earlier instruction causes a first control flow path to be executed. The apparatus also comprises storage circuitry to store the outcome of the later instruction in response to the later instruction completing, and flush circuitry to generate a flush in response to the prediction of the outcome of the earlier instruction being incorrect. Permission circuitry permits the generating of the prediction by the processing circuitry. When re-executing the later instruction in a second control flow path following the flush, the processing circuitry is adapted to perform the generating the prediction of the outcome of the later instruction as the outcome stored in the storage circuitry during execution of the first control flow path. The permission circuitry is adapted to permit or inhibit generating the prediction of the outcome of the later instruction as the outcome stored in the storage circuitry in dependence on a condition.

公开(公告)号：US11138014B2

公开(公告)日：2021-10-05

申请号：US16775431

申请日：2020-01-29

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Houdhaifa Bouzguarrou ,  Thibaut Elie Lanois ,  Guillaume Bolbenes

IPC: G06F9/38 ,  G06F1/03

Abstract: A branch predictor provides a predicted branch instruction outcome for a current block of at least one instruction. The branch predictor comprises branch prediction tables to store branch prediction entries providing branch prediction information; lookup circuitry to perform, based on indexing information associated with the current block, a table lookup in a looked up subset of the branch prediction tables; and prediction generating circuitry to generate the predicted branch instruction outcome for the current block based on the branch prediction information in the branch prediction entries looked up in the looked up subset of branch prediction tables. The looked up subset of branch prediction tables is selected based on lookup filtering information obtained for the current block. Lookups to tables other than the looked up subset are suppressed.

公开(公告)号：US11126714B2

公开(公告)日：2021-09-21

申请号：US16149297

申请日：2018-10-02

Applicant: Arm Limited

Inventor： Alastair David Reid ,  Dominic Phillip Mulligan ,  Milosch Meriac ,  Matthias Lothar Boettcher ,  Nathan Yong Seng Chong ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Frederic Claude Marie Piry ,  Albin Pierrick Tonnerre ,  Thomas Christopher Grocutt ,  Yasuo Ishii

IPC: G06F21/55 ,  H04L9/06 ,  G06F9/38 ,  G06F12/10 ,  G06F21/53 ,  G06F21/78

Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

公开(公告)号：US11003454B2

公开(公告)日：2021-05-11

申请号：US16514124

申请日：2019-07-17

Applicant: Arm Limited

Inventor： Michael Brian Schinzler ,  Michael Filippo ,  Yasuo Ishii

IPC: G06F9/38 ,  G06F9/30

Abstract: Apparatuses for data processing and methods of data processing are provided. A data processing apparatus performs data processing operations in response to a sequence of instructions including performing speculative execution of at least some of the sequence of instructions. In response to a branch instruction the data processing apparatus predicts whether or not the branch is taken or not taken further speculative instruction execution is based on that prediction. A path speculation cost is calculated in dependence on a number of recently flushed instructions and a rate at which speculatively executed instructions are issued may be modified based on the path speculation cost.

公开(公告)号：US12159141B2

公开(公告)日：2024-12-03

申请号：US17949874

申请日：2022-09-21

Applicant: Arm Limited

Inventor： James David Dundas ,  Yasuo Ishii ,  Michael Brian Schinzler

IPC: G06F9/38

Abstract: A data processing apparatus includes control flow prediction circuitry that generates a control flow prediction in respect of a group of one or more instructions. Storage circuitry used by the control flow prediction circuitry stores data in association with groups of instructions used to generate the control flow prediction for each of the groups of instructions. Control flow prediction update circuitry inserts new data into the storage circuitry in association with a new group of one or more instructions in dependence on one or more conditions being met when a miss occurs for the group of one or more instructions in the storage circuitry.