公开(公告)号：US11334361B2

公开(公告)日：2022-05-17

申请号：US16806063

申请日：2020-03-02

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Joseph Michael Pusdesris ,  Muhammad Umar Farooq

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/30

Abstract: An apparatus has processing circuitry, and history storage circuitry to store local history records. Each local history record corresponds to a respective subset of instruction addresses and tracks a sequence of observed instruction behaviour observed for successive instances of instructions having addresses in that subset. Pointer storage circuitry to store a shared pointer shared between the local history records. The shared pointer indicates a common storage position reached in each local history record. Prediction circuitry determines predicted instruction behaviour for a given instruction address based on a selected portion of a selected local history record stored in the history storage circuitry. The prediction circuitry selects the selected local history record based on the given instruction address and selects the selected portion based on the shared pointer.

公开(公告)号：US11263138B2

公开(公告)日：2022-03-01

申请号：US16176686

申请日：2018-10-31

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Miles Robert Dooley ,  Michael Filippo

IPC: G06F12/0862

Abstract: An apparatus is provided that includes cache circuitry that comprises a plurality of cache lines. The cache circuitry treats one or more of the cache lines as trace lines each having correlated addresses and each being tagged by a trigger address. Prefetch circuitry causes data at the correlated addresses stored in the trace lines to be prefetched.

公开(公告)号：US11200177B2

公开(公告)日：2021-12-14

申请号：US16327501

申请日：2016-10-19

Applicant: ARM LIMITED

Inventor： Alex James Waugh ,  Dimitrios Kaseridis ,  Klas Magnus Bruce ,  Michael Filippo ,  Joseph Michael Pusdesris ,  Jamshed Jalal

IPC: G06F12/00 ,  G06F12/121 ,  G06F12/0815

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

公开(公告)号：US10268581B2

公开(公告)日：2019-04-23

申请号：US15479348

申请日：2017-04-05

Applicant: ARM Limited

Inventor： Michael Filippo ,  Klas Magnus Bruce ,  Vasu Kudaravalli ,  Adam George ,  Muhammad Umar Farooq ,  Joseph Michael Pusdesris

IPC: G06F11/10 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0891

Abstract: A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.

公开(公告)号：US11663132B2

公开(公告)日：2023-05-30

申请号：US17500309

申请日：2021-10-13

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Jacob Martin Degasperis ,  Alexander Cole Shulyak

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F12/0238 ,  G06F12/0811 ,  G06F12/1027

Abstract: A technique is provided for prefetching data items. An apparatus has a storage structure with a plurality of entries to store data items. The storage structure is responsive to access requests from processing circuitry to provide access to the data items. The apparatus has prefetch circuitry to prefetch data and correlation information storage to store correlation information for a plurality of data items. The correlation information identifies, for each of the plurality of data items, one or more correlated data items. The prefetch circuitry is configured to monitor the access requests from the processing circuitry. In response to detecting a hit in the correlation information storage for a particular access request that identifies a requested data item for which the correlation information storage stores correlation information, the prefetch circuitry is configured to prefetch the one or more correlated data items identified by the correlation information for the requested data item.

公开(公告)号：US11543994B2

公开(公告)日：2023-01-03

申请号：US17078304

申请日：2020-10-23

Applicant: Arm Limited

Inventor： Ho-Seop Kim ,  Joseph Michael Pusdesris ,  Miles Robert Dooley

IPC: G06F3/06

Abstract: A request node is provided, that includes request circuitry for issuing outgoing memory access requests to a remote node. Status receiving circuitry receives statuses regarding remote memory access requests at the remote node and control circuitry controls at least one of a rate or an aggression at which the outgoing memory access requests are issued to the remote node in dependence on at least some of the statuses. The control circuitry is inhibited from controlling the rate or the aggression until multiple statuses are received.

公开(公告)号：US11442863B2

公开(公告)日：2022-09-13

申请号：US17093792

申请日：2020-11-10

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Adrian Montero ,  Joseph Michael Pusdesris ,  Karthik Sundaram ,  Yasuo Ishii

IPC: G06F12/0862

Abstract: Data processing apparatuses and methods of processing data are disclosed. The operations comprise: storing copies of data items; and storing, in a producer pattern history table, a plurality of producer-consumer relationships, each defining an association between producer load indicator and a plurality of consumer load entries, each consumer load entry comprising a consumer load indicator and one or more usefulness metrics. Further steps comprise: initiating, in response to a data load from an address corresponding to the producer load indicator in the producer pattern history table and when at least one of the corresponding one or more usefulness meets a criterion, a producer prefetch of data to be prefetched for storing as a local copy; and issuing, when the data is returned, one or more consumer prefetches to return consumer data from a consumer address generated from the data returned by the producer prefetch and a consumer load indicator of a consumer load entry.

公开(公告)号：US11157284B1

公开(公告)日：2021-10-26

申请号：US16891431

申请日：2020-06-03

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  Joseph Michael Pusdesris

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus is described, comprising processing circuitry to speculatively execute an earlier instruction and a later instruction by generating a prediction of an outcome of the earlier instruction and a prediction of an outcome of the later instruction, wherein the prediction of the outcome of the earlier instruction causes a first control flow path to be executed. The apparatus also comprises storage circuitry to store the outcome of the later instruction in response to the later instruction completing, and flush circuitry to generate a flush in response to the prediction of the outcome of the earlier instruction being incorrect. Permission circuitry permits the generating of the prediction by the processing circuitry. When re-executing the later instruction in a second control flow path following the flush, the processing circuitry is adapted to perform the generating the prediction of the outcome of the later instruction as the outcome stored in the storage circuitry during execution of the first control flow path. The permission circuitry is adapted to permit or inhibit generating the prediction of the outcome of the later instruction as the outcome stored in the storage circuitry in dependence on a condition.

公开(公告)号：US10713187B2

公开(公告)日：2020-07-14

申请号：US16521621

申请日：2019-07-25

Applicant: ARM Limited

Inventor： Michael Filippo ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Paul Gilbert Meyer ,  David Joseph Hawkins ,  Phanindra Kumar Mannava ,  Joseph Michael Pusdesris

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0831 ,  G06F12/0844

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

公开(公告)号：US12174753B2

公开(公告)日：2024-12-24

申请号：US18253621

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Klas Magnus Bruce ,  Jamshed Jalal ,  Dimitrios Kaseridis ,  Gurunath Ramagiri ,  Ho-Seop Kim ,  Andrew John Turner ,  Rania Hussein Hassan Mameesh

IPC: G06F12/126 ,  G06F12/0811

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.