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公开(公告)号：US20230169908A1
公开(公告)日：2023-06-01
申请号：US17921585
申请日：2021-05-12
Applicant: BOE Technology Group Co., Ltd.
Inventor： Pan XU , Yicheng LIN , Guoying WANG , Xing ZHANG , Ying HAN , Zhan GAO , Dacheng ZHANG
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G2310/0267 , G09G2300/0439
Abstract: A special-shaped display panel includes: a special-shaped display area (S) having gate lines (G), some of the gate lines (G) being cut off in a non-display sub-area (S2) of the special-shaped display area (S); a first gate drive circuit set (A1) located on one side of the special-shaped display area (S), electrically connected to one ends of gate lines (G) which are not cut off by the non-display sub-area (S2), and electrically connected to gate lines (G) on one side which are cut off by the non-display sub-area (S2); and a second gate drive circuit set (A2) located on the other side of the special-shaped display area (S), electrically connected to the other ends of gate lines (G) which are not cut off by the non-display sub-area (S2), and electrically connected gate lines (G) on the other side which are cut off by the non-display sub-area (S2).
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公开(公告)号：US20230165080A1
公开(公告)日：2023-05-25
申请号：US17640230
申请日：2021-01-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Pan XU , Dacheng ZHANG , Xing ZHANG
IPC: H10K59/131 , H10K59/121
CPC classification number: H10K59/131 , H10K59/1213 , H10K59/1216
Abstract: A display substrate and a display device, include: a base substrate, which includes a display area, and a bonding area (BA) disposed on one side of the display area; a plurality of gate lines, a plurality of data lines, a plurality of lead lines, the plurality of lead lines each is respectively electrically connected with a respective one of the plurality of data lines, each of the plurality of lead lines includes a first portion extending in the second direction, and orthographic projections of at least part of the first portions on the base substrate do not overlap with orthographic projections of the data lines on the base substrate.
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公开(公告)号：US20230157110A1
公开(公告)日：2023-05-18
申请号：US16976796
申请日：2019-11-29
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Zhidong YUAN , Meng LI , Dacheng ZHANG , Lang LIU
IPC: H10K59/131
CPC classification number: H10K59/1315
Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a base substrate, a plurality of pixel units and a plurality of gate line groups. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the positions of the sensing transistors are closer to the second gate lines, and the positions of the driving transistors are closer to the first gate line, For two sub-pixels close to each other and located in different pixel units in the same row, at least one signal line has a double-layer alignment structure, and the double-layer alignments are electrically connected with each other.
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44.发明申请公开(公告)号：US20230015542A1
公开(公告)日：2023-01-19
申请号：US17787686
申请日：2021-08-04
Inventor： Ning LIU , Dacheng ZHANG , Cheng XU , Danyang MA , Liusong NI , Jun LIU
Abstract: Provided are an array substrate, a display panel, a display apparatus and a method for manufacturing an array substrate. The array substrate includes: a base substrate; an active layer, which is located on one side of the base substrate, where the active layer includes a channel region, a conductive source region, which is located on one side of the channel region, and a conductive drain region, which is located on the other side of the channel region; and a metal layer, which is located on the side of the active layer that is away from the base substrate, where the metal layer includes a gate electrode and a signal line, which are arranged on the same layer, and the thickness of the gate electrode perpendicular to the base substrate is less than the thickness of the signal line perpendicular to the base substrate.
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公开(公告)号：US20220399523A1
公开(公告)日：2022-12-15
申请号：US16977285
申请日：2019-10-21
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xinwei GAO , Kaihong MA , Dacheng ZHANG , Lang LIU , Chen XU
Abstract: A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel has a display region and a border region that surrounds the display region and includes a peripheral circuit region and a peripheral region; the peripheral circuit region is between the display region and the peripheral region. At least a part of a barrier structure of the display panel is in the peripheral circuit region, and the barrier structure includes an organic barrier layer including an opening passing through the organic barrier layer and an inorganic barrier layer covering the organic barrier layer and filling the opening; an extension direction of the opening is same as that of an edge, close to the opening, of the display panel the peripheral circuit is in the peripheral circuit region.
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Patent Agency Ranking
公开(公告)号：US20220359623A1
公开(公告)日：2022-11-10
申请号：US17869079
申请日：2022-07-20
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Zhidong YUAN , Meng LI , Dacheng ZHANG , Lang LIU
IPC: H01L27/32
Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a first transistor, a second transistor and a storage capacitor. The display substrate further includes an extension portion protruding from the gate electrode of the first transistor, and the extension portion is extended from the gate electrode of the first transistor in the second direction; the extension portion is at least partially overlapped with the first electrode of the second transistor in a direction perpendicular to the base substrate and is electrically connected with the first electrode of the second transistor; in the first direction, the extension portion has a second side closest to the second capacitor electrode, and the second side is recessed in a direction away from the second capacitor electrode.
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公开(公告)号：US20220262890A1
公开(公告)日：2022-08-18
申请号：US17626434
申请日：2021-02-09
Inventor： Leilei CHENG , Yongqian LI , Dacheng ZHANG
IPC: H01L27/32
Abstract: A display substrate includes: a base; a cathode power line disposed on the base and located in the peripheral region; a first insulating layer located on a side of a layer in which the cathode power line is located away from the base and having first via hole(s); a cathode layer located on the first insulating layer and electrically connected to the cathode power line through the first via hole(s); and spacer(s) located on a side of the cathode layer proximate to the base, a spacer covering at least a side wall of a first via hole, a thickness of a portion of the spacer covering the side wall decreasing along the side wall and in a direction pointing from an end of the side wall proximate to the base toward an end of the side wall of the first via hole away from the base.
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公开(公告)号：US20220140018A1
公开(公告)日：2022-05-05
申请号：US17259729
申请日：2020-03-18
Applicant: BOE Technology Group Co., Ltd.
Inventor： Li LIU , Pengcheng LU , Rongrong SHI , Yuanlan TIAN , Junbo WEI , Dacheng ZHANG
Abstract: The present disclosure provides an array substrate including a driving circuit board, and a first electrode layer, an insulating layer, and an anode structure sequentially stacked thereon. The anode structure includes a reflective layer, an intermediate dielectric layer, and a transparent conductive layer sequentially provided in a direction away from the driving circuit board. The array substrate has first, second, and third pixel regions. The anode structure includes first, second, and third anode structures. The first electrode layer includes first, second and third sub-portions. The first, second and third anode structures are coupled with the first, second and third sub-portions through first, second and third via holes in the insulating layer, respectively. A surface of the insulating layer in contact with the first, second and third anode structures is flush; and a thickness of the intermediate dielectric layer in the second, first and third anode structures increases sequentially.
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公开(公告)号：US20210202679A1
公开(公告)日：2021-07-01
申请号：US16977928
申请日：2019-11-29
Inventor： Meng LI , Zhongyuan WU , Yongqian LI , Can YUAN , Zhidong YUAN , Xuehuan FENG , Lang LIU , Dacheng ZHANG
IPC: H01L27/32 , H01L51/52 , H01L51/56 , G09G3/3233
Abstract: A display substrate and a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array. At least one sub-pixel includes a first transistor, a second transistor, a third transistor and a storage capacitor. The first electrode of the third transistor is electrically connected to an active layer of the third transistor through a first via hole, and the first electrode of the third transistor is configured to be electrically connected to the light emitting element through a second via hole; the first via hole and the second via hole are at least partially overlapped with each other in a direction perpendicular to the base substrate.
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公开(公告)号：US20210202605A1
公开(公告)日：2021-07-01
申请号：US16977512
申请日：2019-11-29
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Meng LI , Zhidong YUAN , Dacheng ZHANG , Lang LIU
IPC: H01L27/32
Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.
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