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188 条记录 (耗时 0.027 秒)

    Chemical trim process
    41.
    发明授权
    Chemical trim process 失效
    化学修剪过程

    公开(公告)号：US06492075B1

    公开(公告)日：2002-12-10

    申请号：US09881993

    申请日：2001-06-15

    申请人： Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan

    发明人： Michael K. Templeton ,  Ramkumar Subramanian ,  Bharath Rangarajan

    IPC分类号： G03H900

    CPC分类号： G03F7/40 ,  G03F7/405

    摘要： In one embodiment, the present invention relates to a method of treating a patterned resist involving the steps of providing the patterned resist having structural features of a first size, the patterned resist containing a polymer having a labile group; contacting a coating containing at least one cleaving compound with the patterned resist to form a thin deprotected resist layer at an interface between the patterned resist and the coating; and removing the coating and the thin deprotected resist layer leaving the patterned resist having structural features of a second size, wherein the second size is smaller than the first size.

    摘要翻译： 在一个实施方案中，本发明涉及一种处理图案化抗蚀剂的方法，包括以下步骤：提供具有第一尺寸结构特征的图案化抗蚀剂，所述图案化抗蚀剂含有具有不稳定基团的聚合物; 使含有至少一种裂解化合物的涂层与图案化的抗蚀剂接触以在图案化的抗蚀剂和涂层之间的界面处形成薄的去保护的抗蚀剂层; 以及去除涂层和薄的去保护的抗蚀剂层，留下具有第二尺寸的结构特征的图案化抗蚀剂，其中第二尺寸小于第一尺寸。

    Conducting electron beam resist thin film layer for patterning of mask plates
    42.
    发明授权
    Conducting electron beam resist thin film layer for patterning of mask plates 失效
    用于掩模板图形化的导电电子束抗蚀剂薄膜层

    公开(公告)号：US06482558B1

    公开(公告)日：2002-11-19

    申请号：US09782382

    申请日：2001-02-12

    申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan

    发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan

    IPC分类号： G03F900

    CPC分类号： G03F7/093 ,  G03F1/40 ,  G03F1/50 ,  Y10S430/143

    摘要： One aspect of the present invention relates to a system for dissipating electrostatic charge on a mask plate structure containing the mask plate structure containing a substrate, a chromium layer over the substrate, and a conductive polymer over the chromium layer; a conductive structure coupled to the mask plate structure which allows accumulated electrostatic charge to flow from the mask plate structure; a conductive path between the conductive structure and a ground, wherein the conductive path inacludes a switch controlled by a controller; and a detector coupled to the controller for signaling the controller when the accumulation of electrostatic charge is detected. Another aspect of the present invention relates to a method for dissipating charge accumulation during patterning of mask plates using a conductive polymer layer involving the steps of providing a mask substrate having a chromium layer; depositing a conductive polymer layer over the chromium layer; connecting a conductive structure to the mask substrate; irradiating portions of the mask substrate with an electron beam; detecting whether electrostatic charge exists on the mask substrate; and if electrostatic charge is detected, closing a circuit whereby the conductive structure is grounded to permit a flow of electrostatic charge from the mask substrate to the ground.

    摘要翻译： 本发明的一个方面涉及一种用于在掩模板结构上耗散静电电荷的系统，该系统包含含有衬底的掩模板结构，在衬底上的铬层和在铬层上的导电聚合物; 耦合到掩模板结构的导电结构，其允许积聚的静电电荷从掩模板结构流动; 导电结构和地之间的导电路径，其中导电路径不允许由控制器控制的开关; 以及耦合到控制器的检测器，用于在检测到静电电荷的累积时用于发信号通知控制器。 本发明的另一方面涉及一种使用导电聚合物层在掩模板图案化期间耗散电荷累积的方法，包括以下步骤：提供具有铬层的掩模基板; 在所述铬层上沉积导电聚合物层; 将导电结构连接到所述掩模基板; 用电子束照射掩模基板的部分; 检测在掩模基板上是否存在静电电荷; 并且如果检测到静电电荷，则关闭电路，由此导电结构接地以允许静电电荷从掩模基板流到地面。

    Chemical resist thickness reduction process
    46.
    发明授权
    Chemical resist thickness reduction process 有权
    化学抗蚀剂厚度降低过程

    公开(公告)号：US06274289B1

    公开(公告)日：2001-08-14

    申请号：US09708104

    申请日：2000-11-06

    申请人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Ursula Q. Quinto

    发明人： Ramkumar Subramanian ,  Michael K. Templeton ,  Bharath Rangarajan ,  Ursula Q. Quinto

    IPC分类号： G03F711

    CPC分类号： G03F7/168 ,  G03F7/40

    摘要： In one embodiment, the present invention relates to a method of treating a resist layer involving the steps of providing the resist layer having a first thickness, the resist layer comprising a polymer having a labile group; contacting a coating containing at least one cleaving compound with the resist layer to form a deprotected resist layer at an interface between the resist layer and the coating; and removing the coating and the deprotected resist layer leaving a resist having a second thickness, wherein the second thickness is smaller than the first thickness.

    摘要翻译： 在一个实施方案中，本发明涉及一种处理抗蚀剂层的方法，包括以下步骤：提供具有第一厚度的抗蚀剂层，抗蚀剂层包含具有不稳定基团的聚合物; 使含有至少一种裂解化合物的涂层与抗蚀剂层接触，以在抗蚀剂层和涂层之间的界面处形成去保护的抗蚀剂层; 以及去除涂层和去保护的抗蚀剂层，留下具有第二厚度的抗蚀剂，其中第二厚度小于第一厚度。

    Re-circulation and reuse of dummy-dispensed resist
    48.
    发明授权
    Re-circulation and reuse of dummy-dispensed resist 失效
    虚拟分配抗蚀剂的再循环和再利用

    公开(公告)号：US07153364B1

    公开(公告)日：2006-12-26

    申请号：US10000208

    申请日：2001-10-23

    申请人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Ursula Q. Quinto ,  Michael K. Templeton

    发明人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Ursula Q. Quinto ,  Michael K. Templeton

    IPC分类号： B05B1/28 ,  B05B15/04 ,  B05B3/00

    CPC分类号： H01L21/6715 ,  B05B15/50 ,  B05C11/08

    摘要： The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.

    摘要翻译： 本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法，同时减轻与虚拟分配过程相关的废物。 虚拟分配的抗蚀剂返回到被采集的储存器。 在基板应用之间，分配头可以被定位成将抗蚀剂分配到返回线中。 来自分配头的抗蚀剂的流动在分配头保持抗干燥。 通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中，例如，可以减轻来自虚拟分配过程的废物。

    Dual layer patterning scheme to make dual damascene
    49.
    发明授权
    Dual layer patterning scheme to make dual damascene 失效
    双层图案方案制作双镶嵌

    公开(公告)号：US07078348B1

    公开(公告)日：2006-07-18

    申请号：US09893188

    申请日：2001-06-27

    申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton

    发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Bharath Rangarajan ,  Michael K. Templeton

    IPC分类号： H01L21/302 ,  H01L21/3065

    CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813

    摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.

    摘要翻译： 本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。

    System and method for active control of etch process
    50.
    发明授权
    System and method for active control of etch process 有权
    用于主动控制蚀刻工艺的系统和方法

    公开(公告)号：US07052575B1

    公开(公告)日：2006-05-30

    申请号：US09845454

    申请日：2001-04-30

    申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

    发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

    IPC分类号： C23F1/00

    CPC分类号： H01L21/67253 ,  H01J37/32935 ,  H01L21/67063 ,  H01L22/34

    摘要： A system for regulating an etch process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the acceptability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor selectively controls the etching devices to regulate etching of the portions of the wafer.

    摘要翻译： 提供了一种用于调节蚀刻工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。 所收集的光指示在晶片的相应部分处获得的尺寸。 测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可接受性。 该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。 处理器选择性地控制蚀刻装置来调节晶片的部分的蚀刻。