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公开(公告)号：US12019974B2
公开(公告)日：2024-06-25
申请号：US18334551
申请日：2023-06-14
发明人： Shih-Ming Chang , Shinn-Sheng Yu , Jue-Chin Yu , Ping-Chieh Wu
IPC分类号： G06F30/30 , G03F1/36 , G03F7/00 , G06F30/398
CPC分类号： G06F30/398 , G03F1/36 , G03F7/70433
摘要： A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.
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公开(公告)号：US11940737B2
公开(公告)日：2024-03-26
申请号：US17315087
申请日：2021-05-07
发明人： Hsueh-Yi Chung , Yung-Cheng Chen , Fei-Gwo Tsai , Chi-Hung Liao , Shih-Chi Fu , Wei-Ti Hsu , Jui-Ping Chuang , Tzong-Sheng Chang , Kuei-Shun Chen , Meng-Wei Chen
CPC分类号： G03F7/70433 , G03F1/50 , G03F1/68 , G03F1/70 , G03F1/78 , G03F7/20 , G03F7/70141 , G03F7/70158 , G03F7/70716 , H01L22/30
摘要： A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
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公开(公告)号：US11899373B2
公开(公告)日：2024-02-13
申请号：US18097085
申请日：2023-01-13
发明人： Wen Lo , Shih-Ming Chang
IPC分类号： H01J37/317 , H01J37/304 , G03F7/00
CPC分类号： G03F7/70433 , H01J37/304 , H01J37/3174 , H01J2237/31769
摘要： A method of generating a layout pattern includes determining a first energy density indirectly exposed to a first feature of one or more features of a layout pattern on an energy-sensitive material when the one or more features of the layout pattern on the energy-sensitive material are directly exposed by a charged particle beam. The method also includes adjusting a second energy density exposed the first feature when the first feature is directly exposed by the charged particle beam. A total energy density of the first feature that comprises a sum of the first energy density from the indirect exposure and the second energy density from the direct exposure is maintained at about a threshold energy level to fully expose the first feature in the energy-sensitive material.
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4.发明授权公开(公告)号：US11829074B2
公开(公告)日：2023-11-28
申请号：US17101976
申请日：2020-11-23
发明人： Ralf Lerner
IPC分类号： H01L21/306 , H01L21/48 , H01L21/768 , H01L21/78 , H01L23/498 , H01L23/00 , G03F7/00 , G06F30/392
CPC分类号： G03F7/70433 , G06F30/392 , H01L21/30604 , H01L21/486 , H01L21/76816 , H01L21/7806 , H01L23/49827 , H01L23/49838 , H01L24/00
摘要： The invention relates to a geometric design and corresponding methods for components 22, which are produced on a carrier substrate 10 and prepared by detachment in an etching process 30 for a subsequent absorption and a transfer with a stamp for application to a further substrate. The components 22 are designed in such a way that additional active surfaces are provided for the etching process 30 for undercut the components, so that a faster, more reliable and more homogeneous etching profile is achieved.
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公开(公告)号：US20230375917A1
公开(公告)日：2023-11-23
申请号：US17628484
申请日：2021-08-13
发明人： Xiuxuan ZHANG , Zhineng KONG
CPC分类号： G03F1/74 , G03F1/86 , G03F1/70 , G03F7/70433
摘要： A method and a device for correcting a placement error of a photomask are provided. The method includes: acquiring an exposure offset during a wafer exposure after photomask manufacture is completed, wherein the wafer exposure is a process of forming a circuit pattern on a wafer surface by exposure; and determining a compensation offset for subsequent photomask manufacture according to the exposure offset, to correct a placement error of a photomask, wherein the compensation offset and the exposure offset are vector values that are equal in value and opposite in direction. The method and device for correcting the placement error of the photomask provided in the embodiments of the present disclosure can reduce an overlay error existing in a photolithography process of a semiconductor device by correcting a placement error of a photomask.
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公开(公告)号：US11748551B2
公开(公告)日：2023-09-05
申请号：US17827529
申请日：2022-05-27
发明人： Bing-Siang Chao
IPC分类号： G06F30/398 , G03F7/20 , H01L21/66 , G03F7/00 , G06F111/06 , G06F30/30 , G06F119/18 , G06F119/22
CPC分类号： G06F30/398 , G03F7/705 , G03F7/7065 , G03F7/70433 , G03F7/70491 , G03F7/70616 , H01L22/12 , G06F30/30 , G06F2111/06 , G06F2119/18 , G06F2119/22
摘要： According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.
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公开(公告)号：US11669018B2
公开(公告)日：2023-06-06
申请号：US17338927
申请日：2021-06-04
发明人： Te-Sheng Wang
CPC分类号： G03F7/705 , G03F7/7065 , G03F7/70433 , G03F7/70616
摘要： A method including: simulating an image or characteristics thereof, using characteristics of a design layout and of a patterning process, determining deviations between the image or characteristics thereof and the design layout or characteristics thereof; aligning a metrology image obtained from a patterned substrate and the design layout based on the deviations, wherein the patterned substrate includes a pattern produced from the design layout using the patterning process; and determining a parameter of a patterned substrate from the metrology image aligned with the design layout.
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公开(公告)号：US20230168589A1
公开(公告)日：2023-06-01
申请号：US18097085
申请日：2023-01-13
发明人： Wen LO , Shih-Ming CHANG
IPC分类号： G03F7/20 , H01J37/317 , H01J37/304
CPC分类号： G03F7/70433 , H01J37/3174 , H01J37/304 , H01J2237/31769
摘要： A method of generating a layout pattern includes determining a first energy density indirectly exposed to a first feature of one or more features of a layout pattern on an energy-sensitive material when the one or more features of the layout pattern on the energy-sensitive material are directly exposed by a charged particle beam. The method also includes adjusting a second energy density exposed the first feature when the first feature is directly exposed by the charged particle beam. A total energy density of the first feature that comprises a sum of the first energy density from the indirect exposure and the second energy density from the direct exposure is maintained at about a threshold energy level to fully expose the first feature in the energy-sensitive material.
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公开(公告)号：US20180329310A1
公开(公告)日：2018-11-15
申请号：US15595497
申请日：2017-05-15
发明人： Tamer COSKUN , Thomas L. LAIDIG , Jang Fung CHEN
CPC分类号： G03F7/70433 , G03F1/36 , G03F1/70 , G03F7/0002 , G03F7/705 , G03F2007/2067
摘要： Methods and systems are provided that, in some embodiments, print and process a layer. The layer can be on a wafer or on an application panel. Thereafter, locations of the features that were actually printed and processed are measured. Based upon differences between the measured differences and designed locations for those features at least one distortion model is created. Each distortion model is inverted to create a corresponding correction model. When there are multiple sections, a distortion model and a correction model can be created for each section. Multiple correction models can be combined to create a global correction model.
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公开(公告)号：US10073360B2
公开(公告)日：2018-09-11
申请号：US15541636
申请日：2015-01-28
发明人： Naoyuki Takeda , Shoichi Kuga
CPC分类号： G03F7/70825 , G03F7/2028 , G03F7/7015 , G03F7/70266 , G03F7/70308 , G03F7/70433 , G03F7/708 , G03F7/70808 , H01L21/67259
摘要： An edge exposure apparatus for exposure of an outer circumferential portion of a semiconductor substrate to light includes a light source provided to be able to emit light to the outer circumferential portion and a mirror having a reflection surface arranged to extend in a direction intersecting with an optical axis of light emitted from the light source. The mirror is provided between the outer circumferential portion and a center of the semiconductor substrate in a radial direction of the semiconductor substrate in exposure of the outer circumferential portion of the semiconductor substrate to light.
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