公开(公告)号：US5898841A

公开(公告)日：1999-04-27

申请号：US802003

申请日：1997-02-18

Applicant: Brian Higgins

Inventor： Brian Higgins

IPC: H04L1/00 ,  H04L1/16 ,  H04L1/18 ,  H04L29/06 ,  H04L29/08 ,  G06F13/00

CPC classification number: H04L1/0083 ,  H04L1/1635 ,  H04L1/1657 ,  H04L1/1848 ,  H04L1/189 ,  H04L29/06 ,  H04L1/0001 ,  H04L69/32 ,  H04L69/324 ,  H04L69/326

Abstract: A multi-processor system has a number of processing elements interconnected by a network for transmitting data frames between the elements. Each element includes an application layer, a transport layer and a link layer. The application layer contains end-point processes each having an address space. The transport layer can allocate a buffer in the address space of a specified end-point process and return details of the buffer to the link layer. The link layer can write message data from a received data frame directly into the allocated buffer by direct memory access without buffering the message data in the link layer. In this way, copying is reduced, improving the efficiency of the system.

Abstract translation: 多处理器系统具有通过网络互连的多个处理元件，用于在元件之间传输数据帧。 每个元素包括应用层，传输层和链路层。 应用层包含各自具有地址空间的端点处理。 传输层可以在指定的终点进程的地址空间中分配缓冲区，并将缓冲区的细节返回到链路层。 链路层可以通过直接存储器访问将消息数据从接收到的数据帧直接写入分配的缓冲器，而不会缓冲链路层中的消息数据。 以这种方式，复制减少，提高系统的效率。

公开(公告)号：US5761412A

公开(公告)日：1998-06-02

申请号：US803436

申请日：1997-02-20

Applicant: Brian Higgins

Inventor： Brian Higgins

IPC: G06F9/50 ,  G06F13/00

CPC classification number: G06F9/50 ,  G06F2209/503

Abstract: A multi-processor system has a plurality of processing elements interconnected by a network for transmitting data between the elements. Each of the elements has a status table, indicating that element's view of the statuses of all the elements in the system, and a reliability map, containing a bit for each element in the system, along with copies of the reliability maps of all the other elements in the system. Each element sets the bits in its reliability map to indicate which of the other elements it is in regular communication with. Whenever an element's own reliability map changes, the element sends a copy of that map to all the other elements. Whenever any bit changes in any of the reliability maps held by an element, that element uses the maps to perform a status re-evaluation of all the elements, and updates its status table. This provides a consensus voting mechanism which ensures that all elements arrive at the same view of the element statuses.

Abstract translation: 多处理器系统具有通过网络互连以在元件之间传输数据的多个处理元件。 每个元素都有一个状态表，指示元素对系统中所有元素的状态的视图，以及包含系统中每个元素的位的可靠性图，以及所有其他元素的可靠性映射的副本 系统中的元素。 每个元素设置其可靠性图中的位，以指示与其正常通信的其他元素中的哪一个。 每当元素自己的可靠性图变化时，元素会将该地图的副本发送到所有其他元素。 每当元素持有的任何可靠性图中的任何位发生变化时，该元素使用映射来执行所有元素的状态重新评估，并更新其状态表。 这提供了一个共识投票机制，确保所有元素到达元素状态的相同视图。

公开(公告)号：US5279975A

公开(公告)日：1994-01-18

申请号：US832785

申请日：1992-02-07

Applicant: Kevin M. Devereaux ,  Mark Bunn ,  Brian Higgins

Inventor： Kevin M. Devereaux ,  Mark Bunn ,  Brian Higgins

IPC: G01R31/28 ,  H01L21/66 ,  H01L21/60

CPC classification number: H01L22/20 ,  G01R31/2884 ,  G01R31/2886

Abstract: A method of processing and testing a semiconductor wafer containing an array of integrated circuit dies comprises: a) providing die test cycling circuitry on the wafer b) etching contact openings through a passivation layer atop the wafer to Vcc and Vss pads associated with individual dies; c) patterning a layer of conductive material atop the water to provide a Vcc bus and a Vss bus which interconnect with the Vcc and Vss pads respectively, the Vcc bus electrically connecting with the test cycling circuitry; d) burn-in testing the wafer with selected voltages being applied to the Vss and Vcc buses e) etching the Vcc bus and Vss bus from the wafer; f) etching contact openings through the passivation layer to conductive pads on individual dies; g) testing the individual dies for operability by engaging the conductive pads with testing equipment; h) identifying operable dies; i) singulating the dies; and j) collecting the operable dies.

Abstract translation: 一种处理和测试包含集成电路管芯阵列的半导体晶片的方法，包括：a）在晶片上提供管芯测试循环电路b）蚀刻通过晶片顶部的钝化层的接触开口到与各个管芯相关联的Vcc和Vss焊盘; c）在水面上形成导电材料层，以提供Vcc总线和Vss总线，Vss总线与Vcc和Vss焊盘分别互连，Vcc总线与测试循环电路电连接; d）以选定的电压对Vss和Vcc总线进行老化测试晶片e）从晶片上蚀刻Vcc总线和Vss总线; f）将通过钝化层的接触开口蚀刻到各个管芯上的导电焊盘; g）通过将导电垫与测试设备接合来测试各个模具的可操作性; h）识别可操作的模具; i）分割模具; 和j）收集可操作的模具。