公开(公告)号：US20120155267A1

公开(公告)日：2012-06-21

申请号：US13302285

申请日：2011-11-22

申请人： Francois Abel ,  Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin B. Verrilli

发明人： Francois Abel ,  Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin B. Verrilli

IPC分类号： H04L12/26

CPC分类号： H04L47/6215

摘要： According to embodiments of the invention, there is provided a method, a system, and a computer program product for operating a network processor. The network processor processing a received data packet by reading a flow identification in the data packet; determining a quality of service criteria (QoSC) for the data packet; mapping the flow identification and the QoSC into an index for selecting a receive-queue for routing the data packet; and utilizing the index to route the data packet to the receive-queue.

摘要翻译： 根据本发明的实施例，提供了一种用于操作网络处理器的方法，系统和计算机程序产品。 网络处理器通过读取数据分组中的流标识来处理接收到的数据分组; 确定数据包的服务质量标准（QoSC）; 将流标识和QoSC映射到用于选择用于路由数据分组的接收队列的索引; 并利用索引将数据包路由到接收队列。

公开(公告)号：US20120151307A1

公开(公告)日：2012-06-14

申请号：US13302688

申请日：2011-11-22

申请人： Francois Abel ,  Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

发明人： Francois Abel ,  Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

IPC分类号： G06F11/00

CPC分类号： H04L1/0079 ,  H04L1/0061 ,  H04L1/0072

摘要： Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.

摘要翻译： 公开了一种用于通过支持第一网络协议和第二网络协议的网络处理器来验证数据分组并利用共享硬件的方法和系统。 网络处理器接收数据包; 识别数据包的网络包协议; 并根据网络分组协议对数据分组进行处理，包括：以第一网络协议特有的第一部分分组长度更新第一寄存器; 用第二网络协议特有的第二部分分组长度更新第二寄存器; 以及用独立于网络协议的字段计算的具有第一校验和的更新第三寄存器。 该系统利用组合来自第一寄存器，第二寄存器和第三寄存器的值的函数产生第二校验和。 系统通过将数据包校验和与第二个校验和进行比较来验证数据包。

公开(公告)号：US07715428B2

公开(公告)日：2010-05-11

申请号：US11669419

申请日：2007-01-31

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC分类号： H04L12/66 ,  H04J3/16 ,  H04J3/22

CPC分类号： H04L47/50

摘要： Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.

摘要翻译： 提供了用于处理数据处理设备之间的通信的机制。 利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。 此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。 多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。 可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

公开(公告)号：US07333493B2

公开(公告)日：2008-02-19

申请号：US10850296

申请日：2004-05-20

申请人： Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken

发明人： Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken

IPC分类号： H04L12/28

CPC分类号： H04L69/166 ,  H04L29/06 ,  H04L69/16

摘要： A method for sequencing delivery of information packets from a router having several processing elements to a receiving processing installation, wherein delivery of the packets must be completed in the order the packets arrive at the router. A linked list of packets is formed in the order they are received at the router, and each packet fragmented into successive fragments. Each fragment is processed at the router. The last fragment of each packet in each linked list is labeled with the sequence in which the packet was received, and enqueued in the order labeled for each last fragment on each linked list. Each fragment of each packet is delivered as processed, except the last fragment of each packet on its linked list to the receiving processor installation, and thereafter, transmitting the final fragment of each packet after processing only if that fragment is at the head of the queue.

摘要翻译： 一种用于将信息分组从具有多个处理元件的路由器传送到接收处理设备的方法，其中分组的传送必须按分组到达路由器的顺序完成。 分组的链表以它们在路由器处接收的顺序形成，并且每个分组被分段成连续的片段。 每个片段在路由器处理。 每个链表中每个数据包的最后一个片段都标有接收数据包的顺序，并按照每个链表上每个最后一个片段标记的顺序排队。 每个分组的每个片段被处理，除了其链接列表上的每个分组的最后片段到接收处理器安装，然后在处理之后仅在该片段位于队列的头部时发送每个分组的最后片段 。

公开(公告)号：US20060251120A1

公开(公告)日：2006-11-09

申请号：US11097608

申请日：2005-04-01

申请人： Ravi Arimilli ,  Claude Basso ,  Jean Calvignac ,  Chih-Jen Chang ,  Philippe Damon ,  Ronald Fuhs ,  Satya Sharma ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli ,  Scott Willenborg

发明人： Ravi Arimilli ,  Claude Basso ,  Jean Calvignac ,  Chih-Jen Chang ,  Philippe Damon ,  Ronald Fuhs ,  Satya Sharma ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli ,  Scott Willenborg

IPC分类号： H04J3/16

CPC分类号： H04L12/413 ,  H04L12/40032 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161 ,  H04L69/324

摘要： An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.

摘要翻译： 公开了一种以太网适配器。 以太网适配器包括多个层，用于允许适配器从处理器接收和发送分组。 多个层包括多路分解机制以允许处理器的划分。 主机以太网适配器（HEA）是集成的以太网适配器，为以太网和TCP加速提供了新的方法。 一组TCP / IP加速功能已经在工具包方法中引入：服务器TCP / IP堆栈在需要时使用这些加速器。 服务器和网络接口控制器之间的接口通过绕过PCI总线进行了简化。 HEA支持网络虚拟化。 HEA可以由多个操作系统共享，提供基本的隔离和保护，而不会影响其性能。

公开(公告)号：US20060233177A1

公开(公告)日：2006-10-19

申请号：US11108485

申请日：2005-04-18

申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

IPC分类号： H04L12/56 ,  H04L12/54

CPC分类号： H04L47/568 ,  H04L45/00 ,  H04L45/60 ,  H04L47/50 ,  H04L47/527

摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.

摘要翻译： 公开了一种用于在网络处理器中调度数据分组的系统和方法。 实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。 在一个实施例中，三入口日历结构提供加权最佳努力调度。 多个不同的流中的每一个具有相关的进度控制块。 计划控制块作为链表存储在先进先出缓冲区中。 通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。 每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。 每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。 当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

公开(公告)号：US20060221977A1

公开(公告)日：2006-10-05

申请号：US11096571

申请日：2005-04-01

申请人： Claude Basso ,  Jean Calvignac ,  Chih-Jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli

发明人： Claude Basso ,  Jean Calvignac ,  Chih-Jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli

IPC分类号： H04L12/56 ,  H04L12/28 ,  H04J3/22 ,  H04J3/16

CPC分类号： H04L45/745 ,  H04L45/00 ,  H04L45/54

摘要： Method and apparatus for implementing use of a network connection table. In one aspect, searching for network connections includes receiving a packet, and zeroing particular fields of connection information from the packet if a new connection is to be established. The connection information is converted to an address for a location in a direct table using a table access process. The direct table stores patterns and reference information for new and existing connections. The connection information is compared with at least one pattern stored in the direct table at the address to find reference information for the received packet.

公开(公告)号：US20050209804A1

公开(公告)日：2005-09-22

申请号：US10802235

申请日：2004-03-17

申请人： Claude Basso ,  Richard Blasiak ,  Philippe Damon ,  Laurent Frelechoux ,  Brahmanand Gorti ,  Bernard Metzler ,  Bay Nguyen ,  Natarajan Vaidhyanathan ,  Colin Verrilli

发明人： Claude Basso ,  Richard Blasiak ,  Philippe Damon ,  Laurent Frelechoux ,  Brahmanand Gorti ,  Bernard Metzler ,  Bay Nguyen ,  Natarajan Vaidhyanathan ,  Colin Verrilli

IPC分类号： G06F11/00

CPC分类号： H04L69/28

摘要： System and method for maintenance and examination of timers for a computer system having connections in a networking system. Timer values in a connection table each indicate a timeout for a timer for a connection, where each connection has multiple timers, and one of the timer values is written to a global timer array for each connection such that the global timer array can be scanned to determine when timeouts occur for active connections. Sparse restart of a timer includes restarting the timer if data is communicated with a connected computer before the timeout occurs and after a predetermined time interval after timer start, and not restarting the timer if data is communicated before the timeout occurs and within the predetermined interval after timer start.

摘要翻译： 用于维护和检查具有网络系统中的连接的计算机系统的定时器的系统和方法。 连接表中的定时器值各自表示连接的定时器的超时，其中每个连接具有多个定时器，并且其中一个定时器值被写入到每个连接的全局定时器阵列，以便可以扫描全局定时器阵列 确定活动连接的超时时间。 定时器的稀疏重新启动包括重新启动定时器，如果数据在超时发生之前与连接的计算机通信，并且在定时器启动之后的预定时间间隔之后重新启动，并且如果在超时发生之前传输数据并且在超时之后的预定时间间隔内，则不重新启动定时器 定时器启动。

公开(公告)号：US06721800B1

公开(公告)日：2004-04-13

申请号：US09546702

申请日：2000-04-10

申请人： Claude Basso ,  Anthony Matteo Gallo ,  Natarajan Vaidhyanathan

发明人： Claude Basso ,  Anthony Matteo Gallo ,  Natarajan Vaidhyanathan

IPC分类号： G06F15173

CPC分类号： H04L45/54 ,  H04L45/00 ,  H04L45/22 ,  H04L45/745

摘要： A system and method for providing the ability for a network processor to select from multiple next hop options for a single forwarding entry and provide the ability to weight the probability of which next hop will be chosen.

摘要翻译： 一种用于提供网络处理器从单个转发条目的多个下一跳选项中进行选择的能力的系统和方法，并提供加权下一跳将被选择的概率的能力。

公开(公告)号：US09088594B2

公开(公告)日：2015-07-21

申请号：US13365679

申请日：2012-02-03

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC分类号： G06F9/30 ,  H04L29/06

CPC分类号： H04L69/12

摘要： A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.

摘要翻译： 提供了一种用于共享由网络处理器的网络适配器中的解析器（解析器路径）使用的通信的机制，用于发送对要由外部协处理器执行的进程的请求。 解析器路径由网络处理器（软件路径）的处理器共享，以将请求发送到外部处理器。 该机制用于软件路径，包括由MMIO访问的控制地址和数据字段的请求邮箱，用于发送两种类型的消息，一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程， 用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。 网络的其他处理器轮询该标志直到设置，并获得协处理器结果的数据字段。