摘要:
A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.
摘要:
A variable frequency down hole drill, includes a drill bit, a reciprocating piston operable to deliver an impact load to the drill bit, and means for changing the frequency with which the piston delivers impact loading to the drill bit, also resulting in a change in overall power of the drill. The means for changing frequency and overall power may operate during continuous operation of the drill. The means for changing the frequency and overall power may include a valve for selectively changing the effective volume of a drive or return chamber, an actuator for changing the timing of placing the drive or return chamber in communication with exhaust, or a system for changing the frequency in response to sensing an predetermined operating parameter of the drill, such as pressure or piston position.
摘要:
A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.
摘要:
A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.
摘要:
A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, (b) for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline; (c) to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer; and (d) to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete. The pipeline exception circuitry is designed to recognize an exception occurring in an instruction after a first side-effect of the instruction has been architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler. Pipeline resumption circuitry is effective, after completion of the software exception handler, to resume execution of the excepted program based on the information in the processor registers. The processor registers of the computer are designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory, the processor registers and general purpose registers of the computer together providing sufficient working storage for execution of the exception handler and resumption of the program, without storing processor state to the main memory.
摘要:
A flame resistant fabric having a high level of pilling resistance and good strength characteristics is described. In addition, a method of making the fabric is also described.
摘要:
Tube insertion devices are configured to allow a user to manually insert a hollow tube into a receiving bore, e.g., a pen tube into the bore of a blank. In some implementations, the devices include (a) a pair of elongated arms, each arm comprising a gripping portion and an insertion portions, each of the insertion portions terminating in a distal tip, and (b) a connecting portion joining the arms such that the arms pivot about the connecting portion in a plane defined by the arms when the gripping portions are pressed together by a user. Each of the insertion portions preferably includes a relatively wider proximal portion and a relatively narrower distal tube-carrying portion, the change in width between the proximal portion and the distal portion defining a stop surface.