公开(公告)号：US20060190899A1

公开(公告)日：2006-08-24

申请号：US10905970

申请日：2005-01-28

申请人： William Migatz ,  Paul Campbell ,  David Hathaway ,  David Kung ,  Ruchir Puri ,  Louise Trevillyan

发明人： William Migatz ,  Paul Campbell ,  David Hathaway ,  David Kung ,  Ruchir Puri ,  Louise Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F1/10

摘要： A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.

摘要翻译： 描述了一种方法，系统和程序产品，用于通过为集成电路中的一组时钟树叶元素中的每一个确定允许的布局区域来在集成电路上生成时钟分配网络。 通过确定和相交不同约束下的一组子区域来生成该允许的放置区域，每个子区域标识其中放置时钟树叶元素的区域以满足相应的约束。 确定子区域的约束包括松弛和拥挤约束形式的时间约束。 在确定了允许的放置区域之后，时钟树叶元素被聚集，并且每个时钟树叶元素被放置在其允许的放置区域内的位置，这使得该聚类的一些成本函数最小化。

公开(公告)号：US20060279334A1

公开(公告)日：2006-12-14

申请号：US11466754

申请日：2006-08-23

申请人： Anthony Correale ,  Rajiv Joshi ,  David Kung ,  Zhigang Pan ,  Ruchir Puri

发明人： Anthony Correale ,  Rajiv Joshi ,  David Kung ,  Zhigang Pan ,  Ruchir Puri

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K19/0948

摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

摘要翻译： 用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。 第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。 第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。 来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。

公开(公告)号：US20050114815A1

公开(公告)日：2005-05-26

申请号：US10720562

申请日：2003-11-24

申请人： Anthony Correale ,  David Kung ,  Douglass Lamb ,  Zhigang Pan ,  Ruchir Puri

发明人： Anthony Correale ,  David Kung ,  Douglass Lamb ,  Zhigang Pan ,  Ruchir Puri

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.

摘要翻译： 一种用于优化多电源集成电路中的电平转换器放置的方法和程序产品。 每个电平转换器被放置在最小功率点以最小化净功率和从第一（低）电压净源通过电平转换器到第二（较高）电压净接收器的过渡延迟。 然后，消除了低效率的电平转换器。 具有低于选定的最小锥度尺寸的扇形锥体的电平转换器被删除，并且删除的电平转换器的低电压源恢复。 接收来自多电平转换器的输入的更高电压电平的电路元件被等效的低电压电路元件代替。 低电压缓冲器驱动电平转换器都由单个所述电平转换器代替。

公开(公告)号：US20050114814A1

公开(公告)日：2005-05-26

申请号：US10720464

申请日：2003-11-24

申请人： Anthony Correale ,  David Kung ,  Douglass Lamb ,  Zhigang Pan ,  Ruchir Puri ,  David Wallach

发明人： Anthony Correale ,  David Kung ,  Douglass Lamb ,  Zhigang Pan ,  Ruchir Puri ,  David Wallach

IPC分类号： G06F17/50 ,  H01L25/00 ,  H01L27/118 ,  H03K19/173

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  G06F2217/78 ,  H01L27/118

摘要： An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

摘要翻译： 一种用于降低IC设计功耗的集成电路（IC）设计，方法和程序产品。 IC以电路行组织。 电路行可以包括由低电压（Vdd）电源供电的低压岛和由高电压（Vdd）供电供电的高电压岛。 包括电池，锁存器和宏的电路元件放置有高电压或低电压岛，以尽量减少IC功率，同时保持整体性能。 电平转换器可以放置高压电路元件。

公开(公告)号：US20070028193A1

公开(公告)日：2007-02-01

申请号：US11460537

申请日：2006-07-27

申请人： Anthony Correale ,  David Kung ,  Douglass Lamb ,  Zhigang Pan ,  Ruchir Puri ,  David Wallach

发明人： Anthony Correale ,  David Kung ,  Douglass Lamb ,  Zhigang Pan ,  Ruchir Puri ,  David Wallach

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  G06F2217/78 ,  H01L27/118

摘要： An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

摘要翻译： 一种用于降低IC设计功耗的集成电路（IC）设计，方法和程序产品。 IC以电路行组织。 电路行可以包括由低电压（Vdd）电源供电的低压岛和由高电压（Vdd）供电供电的高电压岛。 包括电池，锁存器和宏的电路元件放置有高电压或低电压岛，以尽量减少IC功率，同时保持整体性能。 电平转换器可以放置高压电路元件。

公开(公告)号：US20050110519A1

公开(公告)日：2005-05-26

申请号：US10720466

申请日：2003-11-24

申请人： Anthony Correale ,  Rajiv Joshi ,  David Kung ,  Zhigang Pan ,  Ruchir Puri

发明人： Anthony Correale ,  Rajiv Joshi ,  David Kung ,  Zhigang Pan ,  Ruchir Puri

IPC分类号： H03K19/0185 ,  H03K19/0948 ,  H03K19/094

CPC分类号： H03K19/018521 ,  H03K19/0948

摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

摘要翻译： 用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。 第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。 第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。 来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。

公开(公告)号：US20140236880A1

公开(公告)日：2014-08-21

申请号：US13770666

申请日：2013-02-19

申请人： Nancy Yan ,  Min He ,  David Kung

发明人： Nancy Yan ,  Min He ,  David Kung

IPC分类号： G06N5/02

CPC分类号： G06N5/025

摘要： A method and system are presented of automatically suggesting rules for data stored in a table, with the table comprising a plurality of columns. The table is profiled to identify a content type for each of one or more of the plurality of columns. A rule knowledge base is accessed to locate rules specified for identified content types. Then, one or more of the located rules specified for identified content types are presented as suggestions. Acceptance of one or more of the suggested rules is received from a user, and the received validations are stored in the rule knowledge base. The accepted rules are applied to data for quality detection and monitoring. Embodiments are also described where columns are suggested based on a given rule.

摘要翻译： 提供了一种方法和系统，其自动地建议存储在表中的数据的规则，其中该表包括多个列。 对表进行剖析以识别多个列中的一个或多个的每一个的内容类型。 访问规则知识库以查找为标识的内容类型指定的规则。 然后，为确定的内容类型指定的一个或多个定位规则作为建议呈现。 从用户接收到一个或多个建议的规则的接受，并且接收到的验证被存储在规则知识库中。 接受的规则适用于质量检测和监测的数据。 还描述了基于给定规则来建议列的实施例。

公开(公告)号：US08634218B2

公开(公告)日：2014-01-21

申请号：US12587398

申请日：2009-10-06

申请人： David Kung

发明人： David Kung

IPC分类号： H02M7/219

CPC分类号： H02M7/219 ,  H02M7/217 ,  H02M7/2176 ,  H02M2007/2195

摘要： An integrated circuit (IC) comprises a rectifier/regulator circuit coupled to receive an ac source voltage and output a regulated dc voltage. The rectifier/regulator circuit includes first and second switching elements that provide charging current when enabled. The first and second switching elements do not provide charging current when disabled. A sensor circuit is coupled to sense the regulated dc voltage and generate a feedback control signal coupled to the rectifier/regulator circuit that enables the first and second switching elements when the regulated dc voltage is above a target voltage, and disables the first and second switching elements when the regulated dc voltage is below the target voltage.

摘要翻译： 集成电路（IC）包括整流器/调节器电路，其耦合以接收交流电源电压并输出调节的直流电压。 整流器/调节器电路包括当使能时提供充电电流的第一和第二开关元件。 禁用时，第一和第二开关元件不提供充电电流。 传感器电路被耦合以感测调节的直流电压并且产生耦合到整流器/调节器电路的反馈控制信号，其在调节的直流电压高于目标电压时使能第一和第二开关元件，并且禁用第一和第二开关 当调节的直流电压低于目标电压时的元件。

公开(公告)号：US20130166515A1

公开(公告)日：2013-06-27

申请号：US13334135

申请日：2011-12-22

申请人： David Kung ,  Wu Cao ,  Suryanarayana Mangipudi ,  Aun-Khuan Tan

发明人： David Kung ,  Wu Cao ,  Suryanarayana Mangipudi ,  Aun-Khuan Tan

IPC分类号： G06F17/30

CPC分类号： G06Q10/063

摘要： In one embodiment, the method includes profiling a data file comprising one or more fields of data. The one or more fields of data contain an item of data; that is, a character, or group of characters that are related. Further, the method includes generating one or more profiling attributes based on profiling the data file. In an example, the one or more profiling attributes refer to profiling information relating to pattern, structure, content and format of data. Further, the method includes selecting at least one of the generated one or more profiling attributes and generating a validation rule based on the selected at least one profiling attribute.

摘要翻译： 在一个实施例中，该方法包括对包括一个或多个数据字段的数据文件进行分析。 一个或多个数据字段包含一个数据项; 也就是说，一个字符或一组相关的字符。 此外，该方法包括基于对数据文件的分析来生成一个或多个分析属性。 在一个示例中，一个或多个分析属性指的是与数据的模式，结构，内容和格式相关的分析信息。 此外，该方法包括选择生成的一个或多个分析属性中的至少一个，并且基于所选择的至少一个分析属性生成验证规则。

公开(公告)号：US20120146715A1

公开(公告)日：2012-06-14

申请号：US13398116

申请日：2012-02-16

申请人： David Kung ,  Leif Lund

发明人： David Kung ,  Leif Lund

IPC分类号： G05F3/02

CPC分类号： G05F3/30

摘要： A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

摘要翻译： 独立于温度的参考电路包括具有共同耦合的基极的第一和第二双极晶体管。 第一和第二电阻串联耦合在第二双极晶体管的发射极和地之间。 第一和第二电阻器分别具有第一和第二电阻值R1和R2，以及第三和第二温度系数TC3和TC2。 电阻值使得第一和第二双极晶体管的基极 - 发射极之间的电压TC1的温度系数基本上等于TC2×（R2 /（R1 + R2））+ TC3×（R1 /（ R1 + R2）），导致流经第一和第二双极晶体管中的每一个的参考电流在温度上基本恒定。 耦合在第二双极晶体管的节点和集电极之间的第三电阻器具有使得在节点处产生的参考电压在温度上基本恒定的值。