Apparatus and method for positively and subtractively decoding addresses
on a bus
    41.
    发明授权
    Apparatus and method for positively and subtractively decoding addresses on a bus 失效
    用于对总线上的地址进行正负的解码的装置和方法

    公开(公告)号:US5864688A

    公开(公告)日:1999-01-26

    申请号:US684584

    申请日:1996-07-19

    IPC分类号: G06F13/36 G06F13/40 G06F12/00

    CPC分类号: G06F13/4045

    摘要: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

    摘要翻译: 具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。 扩展基座和便携式部分都包括用于将周期从外围部件互连(PCI)总线传递到工业标准架构(ISA)总线的桥接电路。 该桥包括用于控制解码的内部设备和配置寄存器。 用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。 根据对接状态,由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。

    Computer system utilizing two ISA busses coupled to a mezzanine bus
    42.
    发明授权
    Computer system utilizing two ISA busses coupled to a mezzanine bus 失效
    利用耦合到夹层总线的两条ISA总线的计算机系统

    公开(公告)号:US5781748A

    公开(公告)日:1998-07-14

    申请号:US671316

    申请日:1996-07-19

    IPC分类号: G06F13/40 H01J13/00

    CPC分类号: G06F13/4027

    摘要: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

    摘要翻译: 具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。 扩展基座和便携式部分都包括用于将周期从外围部件互连(PCI)总线传递到工业标准架构(ISA)总线的桥接电路。 该桥包括用于控制解码的内部设备和配置寄存器。 用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。 根据对接状态,由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。