公开(公告)号：US10396823B2

公开(公告)日：2019-08-27

申请号：US15703822

申请日：2017-09-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/27 ,  H03M13/11 ,  H03M13/25 ,  H04L1/00

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

公开(公告)号：US10361720B2

公开(公告)日：2019-07-23

申请号：US14717174

申请日：2015-05-20

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/00 ,  H03M13/11 ,  G06F11/10 ,  H03M13/25 ,  H03M13/27

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

公开(公告)号：US10326471B2

公开(公告)日：2019-06-18

申请号：US14717203

申请日：2015-05-20

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/00 ,  H03M13/11 ,  G06F11/10 ,  H03M13/25 ,  H03M13/27

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

公开(公告)号：US10224964B2

公开(公告)日：2019-03-05

申请号：US15426940

申请日：2017-02-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/27 ,  H04L1/00 ,  H03M13/17

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

公开(公告)号：US09705529B2

公开(公告)日：2017-07-11

申请号：US14719598

申请日：2015-05-22

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/11 ,  H03M13/25 ,  H03M13/27

CPC classification number: H03M13/1165 ,  H03M13/255 ,  H03M13/2778

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

公开(公告)号：US09698826B2

公开(公告)日：2017-07-04

申请号：US14718839

申请日：2015-05-21

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/11 ,  H04L1/00 ,  H03M13/25 ,  H03M13/27

CPC classification number: H03M13/1165 ,  H03M13/255 ,  H03M13/2778

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

公开(公告)号：US11722155B2

公开(公告)日：2023-08-08

申请号：US17165614

申请日：2021-02-02

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/27 ,  H03M13/11 ,  H03M13/25 ,  G06F11/10 ,  H03M13/00 ,  H04L1/00 ,  H03M13/53

CPC classification number: H03M13/2792 ,  G06F11/1076 ,  H03M13/1102 ,  H03M13/116 ,  H03M13/1148 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/2778 ,  H03M13/616 ,  H03M13/6552 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0058 ,  H04L1/0071

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

公开(公告)号：US11700015B2

公开(公告)日：2023-07-11

申请号：US17500848

申请日：2021-10-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  G06F11/10

CPC classification number: H03M13/1102 ,  G06F11/1076 ,  H03M13/116 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/2778

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

公开(公告)号：US11581904B2

公开(公告)日：2023-02-14

申请号：US17024517

申请日：2020-09-17

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  G06F11/10

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

公开(公告)号：US11556418B2

公开(公告)日：2023-01-17

申请号：US17060768

申请日：2020-10-01

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  G06F11/22

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.