公开(公告)号：US10409681B2

公开(公告)日：2019-09-10

申请号：US15500067

申请日：2015-01-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Derek Alan Sherlock ,  Harvey Ray

IPC: G06F11/10 ,  G06F11/14 ,  G06F3/06 ,  G06F11/20

Abstract: According to an example, a retransmission sequence involving non-idempotent primitives in a fault-tolerant memory fabric may be modified. For example, a redundancy controller may request a sequence to access a stripe in the fault-tolerant memory fabric, wherein the sequence involves a non-idempotent primitive. In response to determining an expiration of a time threshold for the non-idempotent primitive, the redundancy controller may read other data in other cachelines in the stripe, calculate a new parity value by performing an idempotent exclusive-or primitive on the new data with the other data in the stripe, and write the new parity to the stripe using an idempotent write primitive.

公开(公告)号：US20190065314A1

公开(公告)日：2019-02-28

申请号：US16082262

申请日：2016-03-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Derek Alan Sherlock ,  Harvey Ray

IPC: G06F11/10 ,  G06F11/20 ,  G06F3/06

Abstract: A memory device may operate in multiple modes. In a first mode, writes are not committed. In a second mode, writes are committed.

公开(公告)号：US20180217929A1

公开(公告)日：2018-08-02

申请号：US15746618

申请日：2015-07-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mark David Lillibridge ,  Gary Gostin ,  Paolo Faraboschi ,  Derek Alan Sherlock ,  Harvey Ray

IPC: G06F12/06 ,  G06F3/06

CPC classification number: G06F12/0607 ,  G06F3/0611 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/1016 ,  G06F2212/1024

Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.

公开(公告)号：US20170185343A1

公开(公告)日：2017-06-29

申请号：US15314710

申请日：2014-09-02

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Harvey Ray ,  Gary Gostin ,  Derek Alan Sherlock ,  Gregg B. Lesartre

IPC: G06F3/06

Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.