-
公开(公告)号：US10735030B2
公开(公告)日：2020-08-04
申请号：US15670802
申请日：2017-08-07
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gregg B. Lesartre , Harvey Ray , Kevin L. Miller , Chris Michael Brueggen , Martin Foltin
Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.
-
公开(公告)号：US10540109B2
公开(公告)日：2020-01-21
申请号：US15314710
申请日：2014-09-02
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Harvey Ray , Gary Gostin , Derek Alan Sherlock , Gregg B. Lesartre
Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.
-
公开(公告)号：US11016683B2
公开(公告)日：2021-05-25
申请号：US16707946
申请日：2019-12-09
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Harvey Ray , Gary Gostin , Derek Alan Sherlock , Gregg B. Lesartre
Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.
-
公开(公告)号：US10402287B2
公开(公告)日：2019-09-03
申请号：US15500064
申请日：2015-01-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Derek Alan Sherlock , Harvey Ray , Chris Michael Brueggen
Abstract: According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.
-
公开(公告)号：US10312943B2
公开(公告)日：2019-06-04
申请号：US15468619
申请日：2017-03-24
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gregg B. Lesartre , Craig Warner , Martin Foltin , Chris Michael Brueggen , Brian S. Birk , Harvey Ray
Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.
-
Patent Agency Ranking
公开(公告)号：US20180046576A1
公开(公告)日：2018-02-15
申请号：US15234982
申请日：2016-08-11
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gregg B. Lesartre , Harvey Ray
IPC: G06F12/0802
CPC classification number: G06F12/0893 , G06F12/0246 , G06F2212/1036 , G06F2212/60 , G06F2212/7211 , Y02D10/13
Abstract: In one example in accordance with the present disclosure, a system may include a wear level handler to start a current rotation of a wear level algorithm through a plurality of cache line addresses in a region of memory and a location storer to store a rotation count of the rotation. The system may also include a data mover to move a cache line from the selected cache line address to a gap cache line address corresponding to the additional cache line address and a metadata setter to set a metadata of the gap cache line address to a value corresponding to the current rotation. The system may also include a current position determiner to determine, based on the value of at least one metadata and the rotation count, a current position of the current rotation after a power loss event.
-
公开(公告)号：US10409681B2
公开(公告)日：2019-09-10
申请号：US15500067
申请日：2015-01-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Derek Alan Sherlock , Harvey Ray
Abstract: According to an example, a retransmission sequence involving non-idempotent primitives in a fault-tolerant memory fabric may be modified. For example, a redundancy controller may request a sequence to access a stripe in the fault-tolerant memory fabric, wherein the sequence involves a non-idempotent primitive. In response to determining an expiration of a time threshold for the non-idempotent primitive, the redundancy controller may read other data in other cachelines in the stripe, calculate a new parity value by performing an idempotent exclusive-or primitive on the new data with the other data in the stripe, and write the new parity to the stripe using an idempotent write primitive.
-
公开(公告)号：US20190065314A1
公开(公告)日：2019-02-28
申请号：US16082262
申请日：2016-03-22
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Derek Alan Sherlock , Harvey Ray
Abstract: A memory device may operate in multiple modes. In a first mode, writes are not committed. In a second mode, writes are committed.
-
公开(公告)号：US20190044546A1
公开(公告)日：2019-02-07
申请号：US15670802
申请日：2017-08-07
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gregg B. Lesartre , Harvey Ray , Kevin L. Miller , Chris Michael Brueggen , Martin Foltin
Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.
-
公开(公告)号：US20180276068A1
公开(公告)日：2018-09-27
申请号：US15468619
申请日：2017-03-24
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gregg B. Lesartre , Craig Warner , Martin Foltin , Chris Michael Brueggen , Brian S. Birk , Harvey Ray
CPC classification number: H03M13/2906 , G06F11/1048 , G11C29/52 , G11C2029/0409 , G11C2029/0411
Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.
-
-
-
-
-
-
-
-
-
Search Results
18
records
(took 0.04 seconds)
