Using data compression for faster testing of embedded memory
    41.
    发明授权
    Using data compression for faster testing of embedded memory 有权
    使用数据压缩来更快地测试嵌入式内存

    公开(公告)号:US06950971B2

    公开(公告)日:2005-09-27

    申请号:US09993415

    申请日:2001-11-05

    IPC分类号: G11C29/38 G11C29/00 G11C16/06

    摘要: A memory apparatus is configured by obtaining test information for each of group of memory locations within the memory apparatus, compressing the test information to produced compressed test information and, based on the compressed test information, replacing a group of redundant memory circuits respectively associated with the group of memory locations.

    摘要翻译: 通过获取存储装置内的每组存储器位置的测试信息,对测试信息进行压缩以产生压缩测试信息,并且基于压缩的测试信息,替换分别与该测试信息相关联的一组冗余存储器电路, 一组内存位置。

    Partial refresh for synchronous dynamic random access memory (SDRAM) circuits
    42.
    发明授权
    Partial refresh for synchronous dynamic random access memory (SDRAM) circuits 有权
    同步动态随机存取存储器(SDRAM)电路的部分刷新

    公开(公告)号:US06665224B1

    公开(公告)日:2003-12-16

    申请号:US10153042

    申请日:2002-05-22

    IPC分类号: G11C700

    摘要: A semiconductor dynamic random access memory (DRAM) 300 with a programmable memory refresh counter 345 is presented. The counter 345 permits the specification of portions of the DRAM 300 to be refreshed, saving power and time over DRAMs that refresh the entire memory. The counter 345 may be programmed with a wordline address at the beginning of a block of memory and subsequent refresh operations automatically increment or decrement the value in the counter. Additionally, blocks of the memory not being refreshed can be accessed (written or read), improving the utilization of the memory device.

    摘要翻译: 提出了具有可编程存储器刷新计数器345的半导体动态随机存取存储器(DRAM)300。 计数器345允许更新DRAM 300的部分的指定,从而节省了刷新整个存储器的DRAM的功率和时间。 计数器345可以在存储器块的开始处用字线地址编程,并且随后的刷新操作自动地增加或减少计数器中的值。 此外,可以访问(书写或读取)不刷新的存储器块,从而提高存储器件的利用率。

    Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits
    43.
    发明授权
    Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits 有权
    在具有各自包括局部预充电控制电路的存储体的集成电路存储器件中使用预充电来执行预充电命令的系统和方法

    公开(公告)号:US06661721B2

    公开(公告)日:2003-12-09

    申请号:US10017106

    申请日:2001-12-13

    IPC分类号: G11C700

    CPC分类号: G11C11/4094 G11C7/12

    摘要: A precharge command can be issued to a single bank or a precharge-all command can be issued to all banks of an integrated circuit memory device (e.g., DRAM circuit) at any time during normal operation of the device. Internal circuits are provided to decode the respective commands and send them to the different independent memory banks of the integrated circuit memory device. A local precharge control unit (or circuit) is present inside each of the memory banks that can receive and process the decoded precharge commands. If certain specified timing conditions are met, the local precharge control unit can issue and store a precharge request for a specific bank. The precharge request can be held back until all timing requirements are fulfilled. The precharge request can then be automatically executed.

    摘要翻译: 可以在设备的正常操作期间的任何时间向单个存储体发出预充电命令,或者可以在集成电路存储器件(例如,DRAM电路)的所有存储体中发出预充电命令。 提供内部电路以对相应的命令进行解码并将其发送到集成电路存储器件的不同独立存储体。 在可以接收和处理解码的预充电命令的每个存储体内部存在局部预充电控制单元(或电路)。 如果满足某些指定的定时条件,则本地预充电控制单元可以发出并存储针对特定银行的预充电请求。 预充电请求可以被保留,直到满足所有的时序要求为止。 然后可以自动执行预充电请求。